Message ID | 1432877231-5136-3-git-send-email-zhaoshenglong@huawei.com |
---|---|
State | Superseded |
Headers | show
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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 131si4668131qhw.45.2015.05.28.22.29.18 for <patch@linaro.org> (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 28 May 2015 22:29:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:33519 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <qemu-devel-bounces+patch=linaro.org@nongnu.org>) id 1YyCr8-0007ZB-AF for patch@linaro.org; Fri, 29 May 2015 01:29:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <zhaoshenglong@huawei.com>) id 1YyCq8-0006Ll-IZ for qemu-devel@nongnu.org; Fri, 29 May 2015 01:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <zhaoshenglong@huawei.com>) id 1YyCq4-0005D6-6A for qemu-devel@nongnu.org; Fri, 29 May 2015 01:28:16 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:21638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from <zhaoshenglong@huawei.com>) id 1YyCq3-0005CQ-J1; Fri, 29 May 2015 01:28:12 -0400 Received: from 172.24.2.119 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BGS73940; Fri, 29 May 2015 13:28:01 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.158.1; Fri, 29 May 2015 13:27:52 +0800 From: Shannon Zhao <zhaoshenglong@huawei.com> To: <qemu-devel@nongnu.org> Date: Fri, 29 May 2015 13:27:00 +0800 Message-ID: <1432877231-5136-3-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1432877231-5136-1-git-send-email-zhaoshenglong@huawei.com> References: <1432877231-5136-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.5567F8E2.0072, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6daa249d248493ef30deed59c7332ea9 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.66 Cc: qemu-trivial@nongnu.org, pbonzini@redhat.com, mjt@tls.msk.ru, shannon.zhao@linaro.org, peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH v2 02/13] hw/isa/lpc_ich9.c: Fix misusing qemu_allocate_irqs for single irq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: <patchwork-forward.linaro.org> List-Unsubscribe: <mailto:googlegroups-manage+836684582541+unsubscribe@googlegroups.com>, <http://groups.google.com/a/linaro.org/group/patchwork-forward/subscribe> List-Archive: <http://groups.google.com/a/linaro.org/group/patchwork-forward/> List-Post: <http://groups.google.com/a/linaro.org/group/patchwork-forward/post>, <mailto:patchwork-forward@linaro.org> List-Help: <http://support.google.com/a/linaro.org/bin/topic.py?topic=25838>, <mailto:patchwork-forward+help@linaro.org> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. 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diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index dba7585..144b210 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -360,11 +360,8 @@ static void ich9_set_sci(void *opaque, int irq_num, int level) void ich9_lpc_pm_init(PCIDevice *lpc_pci) { ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); - qemu_irq *sci_irq; - - sci_irq = qemu_allocate_irqs(ich9_set_sci, lpc, 1); - ich9_pm_init(lpc_pci, &lpc->pm, sci_irq[0]); + ich9_pm_init(lpc_pci, &lpc->pm, qemu_allocate_irq(ich9_set_sci, lpc, 0)); ich9_lpc_reset(&lpc->d.qdev); }