| Message ID | 1432629650-19559-1-git-send-email-linus.walleij@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On Tue, May 26, 2015 at 11:37 AM, Liviu Dudau <Liviu.Dudau@arm.com> wrote: > I'm going to do a test on my board once I find a bit of spare time > as I have some in-house reports that the handling of the GPIO > buttons is not reliable and on some boards it led to board reset. > Firmware might have been updated since (last year) so it would be > useful if you can tell me the version(s) of firmware that you are > using. ARM V2M-Juno Boot loader v1.0.0 HBI0262 build 616 ARM V2M_Juno Firmware v1.1.8 Build Date: Jun 17 2014 Time : 12:23:19 Date : 27:05:2015 Cmd> reboot This? Yours, Linus Walleij
On Wed, May 27, 2015 at 4:40 PM, Liviu Dudau <Liviu.Dudau@arm.com> wrote: > Also useful if you can capture the text printed by BL1 when booting (depending > on which version you have there might not be much). Oh that is just the v1.1 tag. INFO: BL1: 0x403a000 - 0x403d000 [size = 12288] NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.1(debug):68fc81743e86 NOTICE: BL1: Built : 14:03:21, May 26 2015 INFO: BL1: RAM 0x403a000 - 0x403d000 INFO: Using FIP INFO: Loading file 'bl2.bin' at address 0x4017000 INFO: File 'bl2.bin' loaded: 0x4017000 - 0x401c008 NOTICE: BL1: Booting BL2 INFO: BL1: BL2 address = 0x4017000 INFO: BL1: BL2 spsr = 0x3c5 NOTICE: BL2: v1.1(debug):68fc81743e86 NOTICE: BL2: Built : 14:03:22, May 26 2015 INFO: BL2: Loading BL3-0 INFO: Using FIP INFO: Loading file 'bl30.bin' at address 0x4023000 INFO: Skip reserving memory: 0x4023000 - 0x402e144 INFO: File 'bl30.bin' loaded: 0x4023000 - 0x402e144 INFO: BL2: BL3-0 transferred to SCP INFO: BL2: Loading BL3-1 INFO: Using FIP INFO: Loading file 'bl31.bin' at address 0x4023000 INFO: File 'bl31.bin' loaded: 0x4023000 - 0x402b010 INFO: BL2: Loading BL3-2 INFO: Using FIP WARNING: Failed to access image 'bl32.bin' (-1) WARNING: Failed to load BL3-2 (-1) INFO: BL2: Loading BL3-3 INFO: Using FIP INFO: Loading file 'bl33.bin' at address 0xe0000000 INFO: File 'bl33.bin' loaded: 0xe0000000 - 0xe0035068 NOTICE: BL1: Booting BL3-1 INFO: BL1: BL3-1 address = 0x4023000 INFO: BL1: BL3-1 spsr = 0x3cd INFO: BL1: BL3-1 params address = 0x401c8a0 INFO: BL1: BL3-1 plat params address = 0xf1e2d3c4b5a6978 NOTICE: BL3-1: v1.1(debug):68fc81743e86 NOTICE: BL3-1: Built : 14:03:24, May 26 2015 INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address = 0xe0000000 INFO: BL3-1: Next image spsr = 0x3c9 Do you want me to test on some older version of TF? > UEFI firmware (version a4c2dfb284a55e73f34c48f5944a438006384f04 built at 17:44:48 on Jan 13 2015) I'm using U-Boot, of course ;) Yours, Linus Walleij
On Mon, Jun 1, 2015 at 6:43 PM, Liviu Dudau <Liviu.Dudau@arm.com> wrote: > On Mon, Jun 01, 2015 at 10:02:10AM +0100, Linus Walleij wrote: > I have tested the patches on my Juno R0, so you can add my > > Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> OK thanks! >> > UEFI firmware (version a4c2dfb284a55e73f34c48f5944a438006384f04 built at 17:44:48 on Jan 13 2015) >> >> I'm using U-Boot, of course ;) > > Should I, too? :) I think it's very convenient especially if you just want to boot the kernel off TFTP like with most reference designs. I compile a U-Boot with a command string like so as default: set serverip 192.168.1.32 ; set ipaddr 192.168.1.35 ; tftpboot 0x80000000 Image ; tftpboot 0x83000000 juno.dtb ; booti 0x80000000 - 0x83000000 Then I can just compile a kernel I want to test and reboot and it will download and boot whatever I just compiled quick and nice with no keyboard interaction. http://www.df.lth.se/~triad/krad/junoboard/ Yours, Linus Walleij
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index 351c95bda89e..fde0cfad09de 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -54,6 +54,55 @@ regulator-always-on; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@1 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <116>; + label = "POWER"; + gpios = <&iofpga_gpio0 0 0x4>; + }; + button@2 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <102>; + label = "HOME"; + gpios = <&iofpga_gpio0 1 0x4>; + }; + button@3 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <152>; + label = "RLOCK"; + gpios = <&iofpga_gpio0 2 0x4>; + }; + button@4 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <115>; + label = "VOL+"; + gpios = <&iofpga_gpio0 3 0x4>; + }; + button@5 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <114>; + label = "VOL-"; + gpios = <&iofpga_gpio0 4 0x4>; + }; + button@6 { + debounce_interval = <50>; + wakeup = <1>; + linux,code = <99>; + label = "NMI"; + gpios = <&iofpga_gpio0 5 0x4>; + }; + }; + ethernet@2,00000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x00000000 0x10000>; @@ -148,5 +197,17 @@ clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; }; + + iofpga_gpio0: gpio@1d0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1d0000 0x1000>; + interrupts = <6>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; };
The Juno board has two keys connected to a PL061 GPIO block, in accordance to DDI0524B "ARM Versatile Express Juno Development Platform" revision 1.0, table 2-4 "GPIO (0) and GPIO (1) used for additional user key entry". By trial-and-error I found that these are connected to the two keys named "power" and "home" on the motherboard. Register the GPIO block and these two keys in the device tree using the PL061 GPIO driver and the generic gpio keys. - Map POWER, HOME, VOL+ and VOL- to the obvious input events. - Map RLOCK to KEY_SCREENLOCK/KEY_COFFEE unless someone can explain better what this is for. - Map the NMI button to KEY_SYSREQ as this is used like so in the SYSREQ debugging hack. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- ChangeLog v1->v2: - Register the GPIO block at 0x1d0000 as gpio0, as it turns out there is an unused GPIO block at 0x1e0000 as well. - Label using capital letters. - Map all 6 keys. Only the two highest GPIO lines are unused. - Daniel: please look at this: the Juno has an NMI button, not on the primary IRQ controller (GIC) but on a cascaded GPIO controller. I have waited for this to happen, what are your thoughts about the possibilities to handle this with the priority-escalation trick you were devising for GIC's with FIQ stolen by TrustZone? As the Juno is a typical server design I suspect this is what we have to deal with for the "server-with-an-NMI-pushbutton" use case. --- arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 61 +++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)