diff mbox series

[v4] arm64: dts: rockchip: Add VPU support for the PX30

Message ID 20210728230040.17368-1-ezequiel@collabora.com
State New
Headers show
Series [v4] arm64: dts: rockchip: Add VPU support for the PX30 | expand

Commit Message

Ezequiel Garcia July 28, 2021, 11 p.m. UTC 
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU.
Describe these two entities in device-tree.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
---
Changes from v3:
  * Drop interrupt-names in the iommu.

Heiko, please pick this one via your tree.

The driver and dt-binding patches are already in the media-next tree,
git://linuxtv.org/mchehab/media-next.git.

 arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Heiko Stübner July 29, 2021, 1:19 p.m. UTC | #1 
On Wed, 28 Jul 2021 20:00:40 -0300, Ezequiel Garcia wrote:
> The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU.

> Describe these two entities in device-tree.


Applied, thanks!

[1/1] arm64: dts: rockchip: Add VPU support for the PX30
      commit: 10c68d1788eb29b69b96b5da12c673576922a267

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 248ebb61aa79..fb3f175d25e5 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1024,6 +1024,28 @@  gpu: gpu@ff400000 {
 		status = "disabled";
 	};
 
+	vpu: video-codec@ff442000 {
+		compatible = "rockchip,px30-vpu";
+		reg = <0x0 0xff442000 0x0 0x800>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vepu", "vdpu";
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clock-names = "aclk", "hclk";
+		iommus = <&vpu_mmu>;
+		power-domains = <&power PX30_PD_VPU>;
+	};
+
+	vpu_mmu: iommu@ff442800 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff442800 0x0 0x100>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		power-domains = <&power PX30_PD_VPU>;
+	};
+
 	dsi: dsi@ff450000 {
 		compatible = "rockchip,px30-mipi-dsi";
 		reg = <0x0 0xff450000 0x0 0x10000>;