Message ID | 1432002249-5713-1-git-send-email-heyi.guo@linaro.org |
---|---|
State | New |
Headers | show
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diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index 77a96ec..2398ba2 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -51,8 +51,8 @@ #define TT_ALIGNMENT_BLOCK_ENTRY BIT12 #define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12 -#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFULL << 12) -#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFULL << 12) +#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12) +#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12) #define TT_TYPE_MASK 0x3 #define TT_TYPE_TABLE_ENTRY 0x3
The VA address space has a maximum address width of 48 bits in AArch64 state; 48 bits address width limit will provide better compatibility than 40 bits for future CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> --- ArmPkg/Include/Chipset/AArch64Mmu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)