| Message ID | 20210726035143.53132-1-samuel@sholland.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] dt-bindings: watchdog: sunxi: Add compatible for R329 | expand |
Hi, On Sun, Jul 25, 2021 at 10:51:41PM -0500, Samuel Holland wrote: > On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) > divided by 750. However, starting with R329, LOSC (OSC32k) is added as > an alternative clock source, with a bit to switch between them. > > Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the > cycle counts to keep the timeouts independent of the clock source. This > keeps the programming interface backward-compatible. > > R329 also adds two new registers, to allow software to immediately drive > the SoC reset signal. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > .../watchdog/allwinner,sun4i-a10-wdt.yaml | 30 ++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml > index 9aa3c313c49f..853ceb1b7c0f 100644 > --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml > +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml > @@ -24,6 +24,7 @@ properties: > - allwinner,sun50i-a100-wdt > - allwinner,sun50i-h6-wdt > - allwinner,sun50i-h616-wdt > + - allwinner,sun50i-r329-wdt > - const: allwinner,sun6i-a31-wdt > - items: > - const: allwinner,suniv-f1c100s-wdt > @@ -33,7 +34,16 @@ properties: > maxItems: 1 > > clocks: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 > + > + clock-names: > + minItems: 1 > + maxItems: 2 > + items: > + enum: > + - hosc > + - losc So I assume that the expectations are that hosc is first (or the only valid choice with older SoCs), and losc second? If so, we should make it clear using two const instead of an enum. Here you state that on older SoCs we could use either the hosc or losc clocks as source, which is incorrect. I guess adding descriptions for clocks would be great too. Maxime
diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 9aa3c313c49f..853ceb1b7c0f 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -24,6 +24,7 @@ properties: - allwinner,sun50i-a100-wdt - allwinner,sun50i-h6-wdt - allwinner,sun50i-h616-wdt + - allwinner,sun50i-r329-wdt - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt @@ -33,7 +34,16 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - hosc + - losc interrupts: maxItems: 1 @@ -44,6 +54,24 @@ required: - clocks - interrupts +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-wdt + +then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - clock-names + unevaluatedProperties: false examples:
On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) divided by 750. However, starting with R329, LOSC (OSC32k) is added as an alternative clock source, with a bit to switch between them. Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the cycle counts to keep the timeouts independent of the clock source. This keeps the programming interface backward-compatible. R329 also adds two new registers, to allow software to immediately drive the SoC reset signal. Signed-off-by: Samuel Holland <samuel@sholland.org> --- .../watchdog/allwinner,sun4i-a10-wdt.yaml | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-)