@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-tsnep.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
new file mode 100644
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * TSN endpoint on Xilinx ZCU104 with Avnet AES-FMC-NETW1-G
+ *
+ * Copyright (C) 2021 Gerhard Engleder <engleder.gerhard@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp-zcu104-revC.dts"
+
+/ {
+ model = "TSN endpoint";
+ compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC",
+ "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ amba: axi {
+ tnsep0: ethernet@a0000000 {
+ compatible = "engleder,tsnep";
+ reg = <0x0 0xa0000000 0x0 0x10000>;
+ interrupts = <0 89 1>;
+ interrupt-parent = <&gic>;
+ local-mac-address = [00 00 00 00 00 00];
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ rxc-skew-ps = <1080>;
+ };
+ };
+
+ tsnep1: ethernet@a0010000 {
+ compatible = "engleder,tsnep";
+ reg = <0x0 0xa0010000 0x0 0x10000>;
+ interrupts = <0 90 1>;
+ interrupt-parent = <&gic>;
+ local-mac-address = [00 00 00 00 00 00];
+ phy-mode = "rgmii";
+ phy-handle = <&phy2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@1 {
+ reg = <1>;
+ rxc-skew-ps = <1080>;
+ };
+ };
+ };
+};
Combination of Xilinx ZCU104 with Avnet AES-FMC-NETW1-G and TSN endpoint Ethernet MAC implemented in FPGA. Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com> --- arch/arm64/boot/dts/xilinx/Makefile | 1 + arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts | 50 +++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-tsnep.dts