diff mbox series

[1/2,v2] bus: ixp4xx: Add DT bindings for the IXP4xx expansion bus

Message ID 20210722084330.1618239-1-linus.walleij@linaro.org
State New
Headers show
Series [1/2,v2] bus: ixp4xx: Add DT bindings for the IXP4xx expansion bus | expand

Commit Message

Linus Walleij July 22, 2021, 8:43 a.m. UTC
This adds device tree bindings for the IXP4xx expansion bus controller.

Cc: Marc Zyngier <maz@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

---
ChangeLog v1->v2:
- Drop unevaluatedProperties: false from the node match.
  additionalProperties: true will be the default.
---
 ...intel,ixp4xx-expansion-bus-controller.yaml | 149 ++++++++++++++++++
 1 file changed, 149 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

-- 
2.31.1

Comments

Rob Herring (Arm) July 23, 2021, 8:42 p.m. UTC | #1
On Thu, 22 Jul 2021 10:43:30 +0200, Linus Walleij wrote:
> This adds device tree bindings for the IXP4xx expansion bus controller.

> 

> Cc: Marc Zyngier <maz@kernel.org>

> Cc: devicetree@vger.kernel.org

> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

> ---

> ChangeLog v1->v2:

> - Drop unevaluatedProperties: false from the node match.

>   additionalProperties: true will be the default.

> ---

>  ...intel,ixp4xx-expansion-bus-controller.yaml | 149 ++++++++++++++++++

>  1 file changed, 149 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

> 


AFAICT, there is no patch 2/2. If there is it never made the lists.

Applied, thanks!
Linus Walleij July 23, 2021, 10:42 p.m. UTC | #2
On Fri, Jul 23, 2021 at 10:42 PM Rob Herring <robh@kernel.org> wrote:
> On Thu, 22 Jul 2021 10:43:30 +0200, Linus Walleij wrote:

> > This adds device tree bindings for the IXP4xx expansion bus controller.

> >

> > Cc: Marc Zyngier <maz@kernel.org>

> > Cc: devicetree@vger.kernel.org

> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

> > ---

> > ChangeLog v1->v2:

> > - Drop unevaluatedProperties: false from the node match.

> >   additionalProperties: true will be the default.

> > ---

> >  ...intel,ixp4xx-expansion-bus-controller.yaml | 149 ++++++++++++++++++

> >  1 file changed, 149 insertions(+)

> >  create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

>

> AFAICT, there is no patch 2/2. If there is it never made the lists.


I have the habit of occasionally just resending the patch that changed.
Maybe this is a bad habit :/

> Applied, thanks!


Please drop it if you can, I found problems with the bindings...
It's always more complex.

If it's hard to drop I can also make an incremental patch.

Yours,
Linus Walleij
Rob Herring (Arm) July 27, 2021, 2:05 p.m. UTC | #3
On Fri, Jul 23, 2021 at 4:42 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>

> On Fri, Jul 23, 2021 at 10:42 PM Rob Herring <robh@kernel.org> wrote:

> > On Thu, 22 Jul 2021 10:43:30 +0200, Linus Walleij wrote:

> > > This adds device tree bindings for the IXP4xx expansion bus controller.

> > >

> > > Cc: Marc Zyngier <maz@kernel.org>

> > > Cc: devicetree@vger.kernel.org

> > > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

> > > ---

> > > ChangeLog v1->v2:

> > > - Drop unevaluatedProperties: false from the node match.

> > >   additionalProperties: true will be the default.

> > > ---

> > >  ...intel,ixp4xx-expansion-bus-controller.yaml | 149 ++++++++++++++++++

> > >  1 file changed, 149 insertions(+)

> > >  create mode 100644 Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml

> >

> > AFAICT, there is no patch 2/2. If there is it never made the lists.

>

> I have the habit of occasionally just resending the patch that changed.

> Maybe this is a bad habit :/


It is especially without being a reply to the last version as lore
can't find it. Sending as a reply is not well liked either. So just
send the whole thing.

> > Applied, thanks!

>

> Please drop it if you can, I found problems with the bindings...

> It's always more complex.


Dropped.

Rob
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
new file mode 100644
index 000000000000..58264b9b2f4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml
@@ -0,0 +1,149 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel IXP4xx Expansion Bus Controller
+
+description: |
+  The IXP4xx expansion bus controller handles access to devices on the
+  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
+  including IXP42x, IXP43x, IXP45x and IXP46x.
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+  $nodename:
+    pattern: '^bus@[0-9a-f]+$'
+
+  compatible:
+    enum:
+      - intel,ixp42x-expansion-bus-controller
+      - intel,ixp43x-expansion-bus-controller
+      - intel,ixp45x-expansion-bus-controller
+      - intel,ixp46x-expansion-bus-controller
+
+  reg:
+    description: Control registers for the expansion bus, these are not
+      inside the memory range handled by the expansion bus.
+    maxItems: 1
+
+  "#address-cells":
+    description: |
+      The first cell is the chip select numer.
+      The second cell is the address offset within the bank.
+    const: 2
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+  dma-ranges: true
+
+patternProperties:
+  "^.*@[0-7],[0-9a-f]+$":
+    description: Devices attached to chip selects are represented as
+      subnodes.
+    type: object
+
+    properties:
+      intel,ixp4xx-eb-t1:
+        description: Address timing, extend address phase with n cycles.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 3
+
+      intel,ixp4xx-eb-t2:
+        description: Setup chip select timing, extend setup phase with n cycles.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 3
+
+      intel,ixp4xx-eb-t3:
+        description: Strobe timing, extend strobe phase with n cycles.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 15
+
+      intel,ixp4xx-eb-t4:
+        description: Hold timing, extend hold phase with n cycles.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 3
+
+      intel,ixp4xx-eb-t5:
+        description: Recovery timing, extend recovery phase with n cycles.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 15
+
+      intel,ixp4xx-eb-cycle-type:
+        description: The type of cycles to use on the expansion bus for this
+          chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [0, 1, 2]
+
+      intel,ixp4xx-eb-byte-access-on-halfword:
+        description: Allow byte read access on half word devices.
+        $ref: /schemas/types.yaml#/definitions/flag
+
+      intel,ixp4xx-eb-hpi-hrdy-pol-high:
+        description: Set HPI HRDY polarity to active high when using HPI.
+        $ref: /schemas/types.yaml#/definitions/flag
+
+      intel,ixp4xx-eb-mux-address-and-data:
+        description: Multiplex address and data on the data bus.
+        $ref: /schemas/types.yaml#/definitions/flag
+
+      intel,ixp4xx-eb-ahb-split-transfers:
+        description: Enable AHB split transfers.
+        $ref: /schemas/types.yaml#/definitions/flag
+
+      intel,ixp4xx-eb-write-enable:
+        description: Enable write cycles.
+        $ref: /schemas/types.yaml#/definitions/flag
+
+      intel,ixp4xx-eb-byte-access:
+        description: Expansion bus uses only 8 bits. The default is to use
+          16 bits.
+        $ref: /schemas/types.yaml#/definitions/flag
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+  - dma-ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    bus@50000000 {
+        compatible = "intel,ixp42x-expansion-bus-controller";
+        reg = <0xc4000000 0x28>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0x0 0x50000000 0x01000000>,
+                 <1 0x0 0x51000000 0x01000000>;
+        dma-ranges = <0 0x0 0x50000000 0x01000000>,
+                     <1 0x0 0x51000000 0x01000000>;
+        flash@0,0 {
+            compatible = "intel,ixp4xx-flash", "cfi-flash";
+            bank-width = <2>;
+            reg = <0 0x00000000 0x1000000>;
+            intel,ixp4xx-eb-t3 = <3>;
+            intel,ixp4xx-eb-byte-access-on-halfword;
+            intel,ixp4xx-eb-write-enable;
+        };
+        serial@1,0 {
+            compatible = "exar,xr16l2551", "ns8250";
+            reg = <1 0x00000000 0x10>;
+            interrupt-parent = <&gpio0>;
+            interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+            clock-frequency = <1843200>;
+            intel,ixp4xx-eb-t3 = <3>;
+            intel,ixp4xx-eb-cycle-type = <1>;
+            intel,ixp4xx-eb-write-enable;
+            intel,ixp4xx-eb-byte-access;
+        };
+    };