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[PULL,00/17] target-arm queue

Message ID 1430148045-32400-1-git-send-email-peter.maydell@linaro.org
State Not Applicable
Headers show

Pull-request

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150427

Message

Peter Maydell April 27, 2015, 3:20 p.m. UTC
2.4 is not officially open yet (I'm waiting for Michael to post
the actual 2.3 release announcement) but this is lined up
ready, since I'd like to get the memory attributes patches in
sooner rather than later to reduce the risk of conflicts.

-- PMM

The following changes since commit e1a5476354d396773e4c555f126d752d4ae58fa9:

  Open 2.4 development tree (2015-04-25 22:05:07 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150427

for you to fetch changes up to 4eb276408363aef5435a72a8e818f24220b5edd0:

  Allow ARMv8 SCR.SMD updates (2015-04-26 16:49:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * memory system updates to support transaction attributes
 * set user-mode and secure attributes for accesses made by ARM CPUs
 * rename c1_coproc to cpacr_el1
 * adjust id_aa64pfr0 when has_el3 CPU property disabled
 * allow ARMv8 SCR.SMD updates

----------------------------------------------------------------
Greg Bellows (1):
      Allow ARMv8 SCR.SMD updates

Peter Maydell (14):
      memory: Define API for MemoryRegionOps to take attrs and return status
      memory: Replace io_mem_read/write with memory_region_dispatch_read/write
      Make CPU iotlb a structure rather than a plain hwaddr
      Add MemTxAttrs to the IOTLB
      exec.c: Convert subpage memory ops to _with_attrs
      exec.c: Make address_space_rw take transaction attributes
      exec.c: Add new address_space_ld*/st* functions
      exec.c: Capture the memory attributes for a watchpoint hit
      Switch non-CPU callers from ld/st*_phys to address_space_ld/st*
      target-arm: Honour NS bits in page tables
      target-arm: Use correct memory attributes for page table walks
      target-arm: Add user-mode transaction attribute
      target-arm: Use attribute info to handle user-only watchpoints
      target-arm: Check watchpoints against CPU security state

Sergey Fedorov (2):
      target-arm: rename c1_coproc to cpacr_el1
      target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled

 cputlb.c                          |  22 +-
 dma-helpers.c                     |   3 +-
 exec.c                            | 426 ++++++++++++++++++++++++++++++--------
 hw/alpha/dp264.c                  |   9 +-
 hw/alpha/typhoon.c                |   3 +-
 hw/arm/boot.c                     |   6 +-
 hw/arm/highbank.c                 |  12 +-
 hw/arm/pxa2xx.c                   |   2 +-
 hw/dma/pl080.c                    |  20 +-
 hw/dma/sun4m_iommu.c              |   3 +-
 hw/i386/intel_iommu.c             |   3 +-
 hw/mips/mips_jazz.c               |   6 +-
 hw/pci-host/apb.c                 |   3 +-
 hw/pci-host/prep.c                |   6 +-
 hw/pci/msi.c                      |   3 +-
 hw/pci/msix.c                     |   3 +-
 hw/s390x/css.c                    |  19 +-
 hw/s390x/s390-pci-bus.c           |   9 +-
 hw/s390x/s390-pci-inst.c          |  10 +-
 hw/s390x/s390-virtio-bus.c        |  73 ++++---
 hw/s390x/s390-virtio.c            |   4 +-
 hw/s390x/virtio-ccw.c             |  87 +++++---
 hw/sh4/r2d.c                      |   6 +-
 hw/timer/hpet.c                   |   5 +-
 hw/vfio/pci.c                     |  18 +-
 include/exec/cpu-defs.h           |  15 +-
 include/exec/exec-all.h           |   7 +-
 include/exec/memattrs.h           |  45 ++++
 include/exec/memory.h             | 151 +++++++++++++-
 include/qom/cpu.h                 |   2 +
 include/sysemu/dma.h              |   3 +-
 ioport.c                          |  16 +-
 kvm-all.c                         |   3 +-
 memory.c                          | 204 +++++++++++-------
 monitor.c                         |   3 +-
 scripts/coverity-model.c          |   8 +-
 softmmu_template.h                |  38 ++--
 target-arm/cpu.c                  |   7 +-
 target-arm/cpu.h                  |   4 +-
 target-arm/helper.c               | 137 +++++++++---
 target-arm/op_helper.c            |  29 +--
 target-i386/arch_memory_mapping.c |  15 +-
 42 files changed, 1086 insertions(+), 362 deletions(-)
 create mode 100644 include/exec/memattrs.h

Comments

Peter Maydell April 28, 2015, 10:33 a.m. UTC | #1
On 27 April 2015 at 16:20, Peter Maydell <peter.maydell@linaro.org> wrote:
> 2.4 is not officially open yet (I'm waiting for Michael to post
> the actual 2.3 release announcement) but this is lined up
> ready, since I'd like to get the memory attributes patches in
> sooner rather than later to reduce the risk of conflicts.
>
> -- PMM
>
> The following changes since commit e1a5476354d396773e4c555f126d752d4ae58fa9:
>
>   Open 2.4 development tree (2015-04-25 22:05:07 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150427
>
> for you to fetch changes up to 4eb276408363aef5435a72a8e818f24220b5edd0:
>
>   Allow ARMv8 SCR.SMD updates (2015-04-26 16:49:26 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * memory system updates to support transaction attributes
>  * set user-mode and secure attributes for accesses made by ARM CPUs
>  * rename c1_coproc to cpacr_el1
>  * adjust id_aa64pfr0 when has_el3 CPU property disabled
>  * allow ARMv8 SCR.SMD updates
>

Applied, thanks.

-- PMM