diff mbox series

[1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk

Message ID 20210713144621.605140-1-dinguyen@kernel.org
State Accepted
Commit 9d563236cca43fc4fe190b3be173444bd48e2a3b
Headers show
Series [1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk | expand

Commit Message

Dinh Nguyen July 13, 2021, 2:46 p.m. UTC
The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
not the C3.

Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/clk/socfpga/clk-agilex.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Stephen Boyd July 27, 2021, 12:56 a.m. UTC | #1
Quoting Dinh Nguyen (2021-07-13 07:46:19)
> The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,

> not the C3.

> 

> Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")

> Cc: stable@vger.kernel.org

> Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>

> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

> ---


Applied to clk-next
Stephen Boyd July 27, 2021, 12:56 a.m. UTC | #2
Quoting Dinh Nguyen (2021-07-13 07:46:20)
> Correct the s2f_user0_mux clock representation.

> 

> Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")

> Cc: stable@vger.kernel.org

> Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>

> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

> ---


Applied to clk-next
diff mbox series

Patch

diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 1cb21ea79c64..9dffe9ba0e74 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -107,10 +107,10 @@  static const struct clk_parent_data gpio_db_free_mux[] = {
 };
 
 static const struct clk_parent_data psi_ref_free_mux[] = {
-	{ .fw_name = "main_pll_c3",
-	  .name = "main_pll_c3", },
-	{ .fw_name = "peri_pll_c3",
-	  .name = "peri_pll_c3", },
+	{ .fw_name = "main_pll_c2",
+	  .name = "main_pll_c2", },
+	{ .fw_name = "peri_pll_c2",
+	  .name = "peri_pll_c2", },
 	{ .fw_name = "osc1",
 	  .name = "osc1", },
 	{ .fw_name = "cb-intosc-hs-div2-clk",