[11/17] target/riscv: Use gpr_{src,dst} for RVB

Message ID	20210709042608.883256-12-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB Date: Thu, 8 Jul 2021 21:26:02 -0700 Message-Id: <20210709042608.883256-12-richard.henderson@linaro.org> In-Reply-To: <20210709042608.883256-1-richard.henderson@linaro.org> References: <20210709042608.883256-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/riscv: Use tcg_constant_* \| expand [00/17] target/riscv: Use tcg_constant_* [01/17] target/riscv: Use tcg_constant_* [02/17] target/riscv: Introduce gpr_src, gpr_dst [03/17] target/riscv: Use gpr_{src,dst} in shift operations [04/17] target/riscv: Use gpr_{src, dst} in word division operations [05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi [06/17] target/riscv: Use gpr_src in branches [07/17] target/riscv: Use gpr_{src,dst} for integer load/store [08/17] target/riscv: Use gpr_{src, dst} for word shift operations [09/17] target/riscv: Reorg csr instructions [10/17] target/riscv: Use gpr_{src,dst} for RVA [11/17] target/riscv: Use gpr_{src,dst} for RVB [12/17] target/riscv: Use gpr_{src,dst} for RVF [13/17] target/riscv: Use gpr_{src,dst} for RVD [14/17] target/riscv: Tidy trans_rvh.c.inc [15/17] target/riscv: Use gen_arith for mulh and mulhu [16/17] target/riscv: Use gpr_{src,dst} for RVV [17/17] target/riscv: Remove gen_get_gpr

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20210709042608.883256-12-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB
Date: Thu,  8 Jul 2021 21:26:02 -0700
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Series

target/riscv: Use tcg_constant_* | expand

Comments

Alistair Francis July 15, 2021, 4:52 a.m. UTC | #1

On Fri, Jul 9, 2021 at 2:37 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alistair Francis <alistair.francis@wdc.com>


Alistair

> ---

>  target/riscv/insn_trans/trans_rvb.c.inc | 11 ++++-------

>  1 file changed, 4 insertions(+), 7 deletions(-)

>

> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc

> index 9e81f6e3de..58921f3224 100644

> --- a/target/riscv/insn_trans/trans_rvb.c.inc

> +++ b/target/riscv/insn_trans/trans_rvb.c.inc

> @@ -423,16 +423,13 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)

>      REQUIRE_64BIT(ctx);

>      REQUIRE_EXT(ctx, RVB);

>

> -    TCGv source1 = tcg_temp_new();

> -    gen_get_gpr(source1, a->rs1);

> +    TCGv dest = gpr_dst(ctx, a->rd);

> +    TCGv src1 = gpr_src(ctx, a->rs1);

>

>      if (a->shamt < 32) {

> -        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);

> +        tcg_gen_deposit_z_tl(dest, src1, a->shamt, 32);

>      } else {

> -        tcg_gen_shli_tl(source1, source1, a->shamt);

> +        tcg_gen_shli_tl(dest, src1, a->shamt);

>      }

> -

> -    gen_set_gpr(a->rd, source1);

> -    tcg_temp_free(source1);

>      return true;

>  }

> --

> 2.25.1

>

>

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 9e81f6e3de..58921f3224 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -423,16 +423,13 @@  static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVB);
 
-    TCGv source1 = tcg_temp_new();
-    gen_get_gpr(source1, a->rs1);
+    TCGv dest = gpr_dst(ctx, a->rd);
+    TCGv src1 = gpr_src(ctx, a->rs1);
 
     if (a->shamt < 32) {
-        tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
+        tcg_gen_deposit_z_tl(dest, src1, a->shamt, 32);
     } else {
-        tcg_gen_shli_tl(source1, source1, a->shamt);
+        tcg_gen_shli_tl(dest, src1, a->shamt);
     }
-
-    gen_set_gpr(a->rd, source1);
-    tcg_temp_free(source1);
     return true;
 }

[11/17] target/riscv: Use gpr_{src,dst} for RVB

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