diff mbox series

[1/6] clk: uniphier: Add PCIe clock entry

Message ID 1625565671-30022-2-git-send-email-hayashi.kunihiko@socionext.com
State Accepted
Commit a1b4810adbb61acb6d0efe0f7fa0588e476c8647
Headers show
Series uniphier: Add PCIe host controller and Akebi96 board support | expand

Commit Message

Kunihiko Hayashi July 6, 2021, 10:01 a.m. UTC 
Add clock control for PCIe controller on each SoC.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

---
 drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++
 1 file changed, 3 insertions(+)

-- 
2.7.4

Comments

Tom Rini July 14, 2021, 8:52 p.m. UTC | #1 
On Tue, Jul 06, 2021 at 07:01:06PM +0900, Kunihiko Hayashi wrote:

> Add clock control for PCIe controller on each SoC.

> 

> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>


Applied to u-boot/master, thanks!

-- 
Tom
diff mbox series

Patch

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index c627a4b..ff5d364 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -29,6 +29,7 @@  const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(15, 0x2104, 17),	/* usb31 (Pro4, Pro5, PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x2104, 19),	/* usb30-phy (PXs2) */
 	UNIPHIER_CLK_GATE_SIMPLE(20, 0x2104, 20),	/* usb31-phy (PXs2) */
+	UNIPHIER_CLK_GATE_SIMPLE(24, 0x2108, 2),	/* pcie (Pro5) */
 	{ /* sentinel */ }
 #endif
 };
@@ -43,6 +44,7 @@  const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(14, 0x210c, 14),	/* usb30 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(16, 0x210c, 12),	/* usb30-phy0 (LD20) */
 	UNIPHIER_CLK_GATE_SIMPLE(17, 0x210c, 13),	/* usb30-phy1 (LD20) */
+	UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 4),	/* pcie */
 	{ /* sentinel */ }
 #endif
 };
@@ -62,6 +64,7 @@  const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE_SIMPLE(18, 0x210c, 20),	/* usb30-phy2 */
 	UNIPHIER_CLK_GATE_SIMPLE(20, 0x210c, 17),	/* usb31-phy0 */
 	UNIPHIER_CLK_GATE_SIMPLE(21, 0x210c, 19),	/* usb31-phy1 */
+	UNIPHIER_CLK_GATE_SIMPLE(24, 0x210c, 3),	/* pcie */
 	{ /* sentinel */ }
 #endif
 };