| Message ID | 20210705140304.652929-3-benjamin.gaignard@collabora.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support of HDMI for rk3568 | expand |
add algea.cao and andy.yan 在 2021/7/5 22:03, Benjamin Gaignard 写道: > Add a new dw_hdmi_plat_data struct and new compatible for rk3568. > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 28 +++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > index 830bdd5e9b7ce..5817c3a9fe64b 100644 > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > @@ -50,6 +50,10 @@ > #define RK3399_GRF_SOC_CON20 0x6250 > #define RK3399_HDMI_LCDC_SEL BIT(6) > > +#define RK3568_GRF_VO_CON1 0x0364 > +#define RK3568_HDMI_SDAIN_MSK BIT(15) > +#define RK3568_HDMI_SCLIN_MSK BIT(14) > + > #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) > > /** > @@ -467,6 +471,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { > .use_drm_infoframe = true, > }; > > +static struct rockchip_hdmi_chip_data rk3568_chip_data = { > + .lcdsel_grf_reg = -1, > +}; > + > +static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { > + .mode_valid = dw_hdmi_rockchip_mode_valid, > + .mpll_cfg = rockchip_mpll_cfg, > + .cur_ctr = rockchip_cur_ctr, > + .phy_config = rockchip_phy_config, > + .phy_data = &rk3568_chip_data, > + .use_drm_infoframe = true, > +}; > + > static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { > { .compatible = "rockchip,rk3228-dw-hdmi", > .data = &rk3228_hdmi_drv_data > @@ -480,6 +497,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { > { .compatible = "rockchip,rk3399-dw-hdmi", > .data = &rk3399_hdmi_drv_data > }, > + { .compatible = "rockchip,rk3568-dw-hdmi", > + .data = &rk3568_hdmi_drv_data > + }, > {}, > }; > MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); > @@ -536,6 +556,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, > return ret; > } > > + if (hdmi->chip_data == &rk3568_chip_data) { > + regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, > + HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | > + RK3568_HDMI_SCLIN_MSK, > + RK3568_HDMI_SDAIN_MSK | > + RK3568_HDMI_SCLIN_MSK)); > + } > + > hdmi->phy = devm_phy_optional_get(dev, "hdmi"); > if (IS_ERR(hdmi->phy)) { > ret = PTR_ERR(hdmi->phy);
Hi Benjamin, RK3568 hdmi phy ref clock source is HPLL. HPLL must be set when switching resolution or plugging. Whether to add the configuration for HPLL? Thanks! 在 2021/7/5 22:03, Benjamin Gaignard 写道: > Add a new dw_hdmi_plat_data struct and new compatible for rk3568. > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 28 +++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > index 830bdd5e9b7ce..5817c3a9fe64b 100644 > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > @@ -50,6 +50,10 @@ > #define RK3399_GRF_SOC_CON20 0x6250 > #define RK3399_HDMI_LCDC_SEL BIT(6) > > +#define RK3568_GRF_VO_CON1 0x0364 > +#define RK3568_HDMI_SDAIN_MSK BIT(15) > +#define RK3568_HDMI_SCLIN_MSK BIT(14) > + > #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) > > /** > @@ -467,6 +471,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { > .use_drm_infoframe = true, > }; > > +static struct rockchip_hdmi_chip_data rk3568_chip_data = { > + .lcdsel_grf_reg = -1, > +}; > + > +static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { > + .mode_valid = dw_hdmi_rockchip_mode_valid, > + .mpll_cfg = rockchip_mpll_cfg, > + .cur_ctr = rockchip_cur_ctr, > + .phy_config = rockchip_phy_config, > + .phy_data = &rk3568_chip_data, > + .use_drm_infoframe = true, > +}; > + > static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { > { .compatible = "rockchip,rk3228-dw-hdmi", > .data = &rk3228_hdmi_drv_data > @@ -480,6 +497,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { > { .compatible = "rockchip,rk3399-dw-hdmi", > .data = &rk3399_hdmi_drv_data > }, > + { .compatible = "rockchip,rk3568-dw-hdmi", > + .data = &rk3568_hdmi_drv_data > + }, > {}, > }; > MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); > @@ -536,6 +556,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, > return ret; > } > > + if (hdmi->chip_data == &rk3568_chip_data) { > + regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, > + HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | > + RK3568_HDMI_SCLIN_MSK, > + RK3568_HDMI_SDAIN_MSK | > + RK3568_HDMI_SCLIN_MSK)); > + } > + > hdmi->phy = devm_phy_optional_get(dev, "hdmi"); > if (IS_ERR(hdmi->phy)) { > ret = PTR_ERR(hdmi->phy);
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 830bdd5e9b7ce..5817c3a9fe64b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -50,6 +50,10 @@ #define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_HDMI_LCDC_SEL BIT(6) +#define RK3568_GRF_VO_CON1 0x0364 +#define RK3568_HDMI_SDAIN_MSK BIT(15) +#define RK3568_HDMI_SCLIN_MSK BIT(14) + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) /** @@ -467,6 +471,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { .use_drm_infoframe = true, }; +static struct rockchip_hdmi_chip_data rk3568_chip_data = { + .lcdsel_grf_reg = -1, +}; + +static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .phy_data = &rk3568_chip_data, + .use_drm_infoframe = true, +}; + static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3228-dw-hdmi", .data = &rk3228_hdmi_drv_data @@ -480,6 +497,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3399-dw-hdmi", .data = &rk3399_hdmi_drv_data }, + { .compatible = "rockchip,rk3568-dw-hdmi", + .data = &rk3568_hdmi_drv_data + }, {}, }; MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); @@ -536,6 +556,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return ret; } + if (hdmi->chip_data == &rk3568_chip_data) { + regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, + HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK | + RK3568_HDMI_SCLIN_MSK, + RK3568_HDMI_SDAIN_MSK | + RK3568_HDMI_SCLIN_MSK)); + } + hdmi->phy = devm_phy_optional_get(dev, "hdmi"); if (IS_ERR(hdmi->phy)) { ret = PTR_ERR(hdmi->phy);
Add a new dw_hdmi_plat_data struct and new compatible for rk3568. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 28 +++++++++++++++++++++ 1 file changed, 28 insertions(+)