| Message ID | 1624015734-16778-2-git-send-email-okukatla@codeaurora.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add L3 provider support for SC7280 | expand |
Quoting Odelu Kukatla (2021-06-18 04:28:52) > Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++- > include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++- > 2 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > index d6a95c3..9f67c8e 100644 > --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml > @@ -18,12 +18,19 @@ properties: > compatible: > enum: > - qcom,sc7180-osm-l3 > + - qcom,sc7280-epss-l3 > - qcom,sdm845-osm-l3 > - qcom,sm8150-osm-l3 > - qcom,sm8250-epss-l3 > > reg: > - maxItems: 1 > + minItems: 1 > + maxItems: 4 Can we base this on the compatible string so that only sc7280-epss-l3 requires 4 items? and then the others require 1 reg property? > + items: > + - description: OSM clock domain-0 base address and size > + - description: OSM clock domain-1 base address and size > + - description: OSM clock domain-2 base address and size > + - description: OSM clock domain-3 base address and size > > clocks: > items:
Thanks Stephen for the reviews! On 2021-07-09 04:52, Stephen Boyd wrote: > Quoting Odelu Kukatla (2021-06-18 04:28:52) >> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 >> ++++++++- >> include/dt-bindings/interconnect/qcom,osm-l3.h | 10 >> +++++++++- >> 2 files changed, 17 insertions(+), 2 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> index d6a95c3..9f67c8e 100644 >> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml >> @@ -18,12 +18,19 @@ properties: >> compatible: >> enum: >> - qcom,sc7180-osm-l3 >> + - qcom,sc7280-epss-l3 >> - qcom,sdm845-osm-l3 >> - qcom,sm8150-osm-l3 >> - qcom,sm8250-epss-l3 >> >> reg: >> - maxItems: 1 >> + minItems: 1 >> + maxItems: 4 > > Can we base this on the compatible string so that only sc7280-epss-l3 > requires 4 items? and then the others require 1 reg property? > Done, Addressing this in new revision. >> + items: >> + - description: OSM clock domain-0 base address and size >> + - description: OSM clock domain-1 base address and size >> + - description: OSM clock domain-2 base address and size >> + - description: OSM clock domain-3 base address and size >> >> clocks: >> items:
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index d6a95c3..9f67c8e 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -18,12 +18,19 @@ properties: compatible: enum: - qcom,sc7180-osm-l3 + - qcom,sc7280-epss-l3 - qcom,sdm845-osm-l3 - qcom,sm8150-osm-l3 - qcom,sm8250-epss-l3 reg: - maxItems: 1 + minItems: 1 + maxItems: 4 + items: + - description: OSM clock domain-0 base address and size + - description: OSM clock domain-1 base address and size + - description: OSM clock domain-2 base address and size + - description: OSM clock domain-3 base address and size clocks: items: diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h index 61ef649..99534a5 100644 --- a/include/dt-bindings/interconnect/qcom,osm-l3.h +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved. */ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H @@ -11,5 +11,13 @@ #define MASTER_EPSS_L3_APPS 0 #define SLAVE_EPSS_L3_SHARED 1 +#define SLAVE_EPSS_L3_CPU0 2 +#define SLAVE_EPSS_L3_CPU1 3 +#define SLAVE_EPSS_L3_CPU2 4 +#define SLAVE_EPSS_L3_CPU3 5 +#define SLAVE_EPSS_L3_CPU4 6 +#define SLAVE_EPSS_L3_CPU5 7 +#define SLAVE_EPSS_L3_CPU6 8 +#define SLAVE_EPSS_L3_CPU7 9 #endif
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++- include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++- 2 files changed, 17 insertions(+), 2 deletions(-)