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[RFC,v1,157/256] cl8k: add reg/reg_macdsp_api.h

Message ID 20210617160223.160998-158-viktor.barna@celeno.com
State New
Headers show
Series wireless: cl8k driver for Celeno IEEE 802.11ax devices | expand

Commit Message

Viktor Barna June 17, 2021, 4 p.m. UTC 
From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 .../wireless/celeno/cl8k/reg/reg_macdsp_api.h | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h

--
2.30.0
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Patch

diff --git a/drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h b/drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h
new file mode 100644
index 000000000000..434f963650a2
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/reg/reg_macdsp_api.h
@@ -0,0 +1,66 @@ 
+/* SPDX-License-Identifier: MIT */
+/* Copyright(c) 2019-2021, Celeno Communications Ltd. */
+
+#ifndef CL_REG_MACDSP_API_H
+#define CL_REG_MACDSP_API_H
+
+#include <linux/types.h>
+#include "reg/reg_access.h"
+#include "hw.h"
+
+/*
+ * @brief CONFIG_SPACE register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:26 ActiveAntennaSet          0x0
+ *    25:20 RxCckActiveChain          0x0
+ *    19:14 RxOfdmActiveChain         0x0
+ *    13:08 TxCckActiveChain          0x0
+ *    07:06 Band                      0x0
+ *    05:04 ChannelBandwidth          0x0
+ *    03    OfdmOnly                  0
+ *    02    RxSensingMode             0
+ *    01    UpdateSync                0
+ *    00    StartupSync               0
+ * </pre>
+ */
+#define MACDSP_API_CONFIG_SPACE_ADDR        (REG_MACDSP_API_BASE_ADDR + 0x00000010)
+#define MACDSP_API_CONFIG_SPACE_OFFSET      0x00000010
+#define MACDSP_API_CONFIG_SPACE_INDEX       0x00000004
+#define MACDSP_API_CONFIG_SPACE_RESET       0x00000000
+
+static inline void macdsp_api_config_space_set(struct cl_hw *cl_hw, u32 value)
+{
+       cl_reg_write(cl_hw, MACDSP_API_CONFIG_SPACE_ADDR, value);
+}
+
+/*
+ * @brief INBDPOW_20 register definition
+ * <pre>
+ *   Bits           Field Name   Reset Value
+ *  -----   ------------------   -----------
+ *    31:24 Inbdpow20Pdbm3            0x0
+ *    23:16 Inbdpow20Pdbm2            0x0
+ *    15:08 Inbdpow20Pdbm1            0x0
+ *    07:00 Inbdpow20Pdbm0            0x0
+ * </pre>
+ */
+#define MACDSP_API_INBDPOW_20_ADDR        (REG_MACDSP_API_BASE_ADDR + 0x00000974)
+#define MACDSP_API_INBDPOW_20_OFFSET      0x00000974
+#define MACDSP_API_INBDPOW_20_INDEX       0x0000025D
+#define MACDSP_API_INBDPOW_20_RESET       0x00000000
+
+static inline void macdsp_api_inbdpow_20_unpack(struct cl_hw *cl_hw,
+                                               u8 *inbdpow20pdbm3, u8 *inbdpow20pdbm2,
+                                               u8 *inbdpow20pdbm1, u8 *inbdpow20pdbm0)
+{
+       u32 local_val = cl_reg_read(cl_hw, MACDSP_API_INBDPOW_20_ADDR);
+
+       *inbdpow20pdbm3 = (local_val & ((u32)0xFF000000)) >> 24;
+       *inbdpow20pdbm2 = (local_val & ((u32)0x00FF0000)) >> 16;
+       *inbdpow20pdbm1 = (local_val & ((u32)0x0000FF00)) >> 8;
+       *inbdpow20pdbm0 = (local_val & ((u32)0x000000FF)) >> 0;
+}
+
+#endif /* CL_REG_MACDSP_API_H */