new file mode 100644
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_Q6_PRM_H__
+#define __DT_BINDINGS_Q6_PRM_H__
+
+/* Audio Front End (PRM) virtual ports IDs */
+#define HDMI_RX 1
+#define SLIMBUS_0_RX 2
+#define SLIMBUS_0_TX 3
+#define SLIMBUS_1_RX 4
+#define SLIMBUS_1_TX 5
+#define SLIMBUS_2_RX 6
+#define SLIMBUS_2_TX 7
+#define SLIMBUS_3_RX 8
+#define SLIMBUS_3_TX 9
+#define SLIMBUS_4_RX 10
+#define SLIMBUS_4_TX 11
+#define SLIMBUS_5_RX 12
+#define SLIMBUS_5_TX 13
+#define SLIMBUS_6_RX 14
+#define SLIMBUS_6_TX 15
+#define PRIMARY_MI2S_RX 16
+#define PRIMARY_MI2S_TX 17
+#define SECONDARY_MI2S_RX 18
+#define SECONDARY_MI2S_TX 19
+#define TERTIARY_MI2S_RX 20
+#define TERTIARY_MI2S_TX 21
+#define QUATERNARY_MI2S_RX 22
+#define QUATERNARY_MI2S_TX 23
+#define PRIMARY_TDM_RX_0 24
+#define PRIMARY_TDM_TX_0 25
+#define PRIMARY_TDM_RX_1 26
+#define PRIMARY_TDM_TX_1 27
+#define PRIMARY_TDM_RX_2 28
+#define PRIMARY_TDM_TX_2 29
+#define PRIMARY_TDM_RX_3 30
+#define PRIMARY_TDM_TX_3 31
+#define PRIMARY_TDM_RX_4 32
+#define PRIMARY_TDM_TX_4 33
+#define PRIMARY_TDM_RX_5 34
+#define PRIMARY_TDM_TX_5 35
+#define PRIMARY_TDM_RX_6 36
+#define PRIMARY_TDM_TX_6 37
+#define PRIMARY_TDM_RX_7 38
+#define PRIMARY_TDM_TX_7 39
+#define SECONDARY_TDM_RX_0 40
+#define SECONDARY_TDM_TX_0 41
+#define SECONDARY_TDM_RX_1 42
+#define SECONDARY_TDM_TX_1 43
+#define SECONDARY_TDM_RX_2 44
+#define SECONDARY_TDM_TX_2 45
+#define SECONDARY_TDM_RX_3 46
+#define SECONDARY_TDM_TX_3 47
+#define SECONDARY_TDM_RX_4 48
+#define SECONDARY_TDM_TX_4 49
+#define SECONDARY_TDM_RX_5 50
+#define SECONDARY_TDM_TX_5 51
+#define SECONDARY_TDM_RX_6 52
+#define SECONDARY_TDM_TX_6 53
+#define SECONDARY_TDM_RX_7 54
+#define SECONDARY_TDM_TX_7 55
+#define TERTIARY_TDM_RX_0 56
+#define TERTIARY_TDM_TX_0 57
+#define TERTIARY_TDM_RX_1 58
+#define TERTIARY_TDM_TX_1 59
+#define TERTIARY_TDM_RX_2 60
+#define TERTIARY_TDM_TX_2 61
+#define TERTIARY_TDM_RX_3 62
+#define TERTIARY_TDM_TX_3 63
+#define TERTIARY_TDM_RX_4 64
+#define TERTIARY_TDM_TX_4 65
+#define TERTIARY_TDM_RX_5 66
+#define TERTIARY_TDM_TX_5 67
+#define TERTIARY_TDM_RX_6 68
+#define TERTIARY_TDM_TX_6 69
+#define TERTIARY_TDM_RX_7 70
+#define TERTIARY_TDM_TX_7 71
+#define QUATERNARY_TDM_RX_0 72
+#define QUATERNARY_TDM_TX_0 73
+#define QUATERNARY_TDM_RX_1 74
+#define QUATERNARY_TDM_TX_1 75
+#define QUATERNARY_TDM_RX_2 76
+#define QUATERNARY_TDM_TX_2 77
+#define QUATERNARY_TDM_RX_3 78
+#define QUATERNARY_TDM_TX_3 79
+#define QUATERNARY_TDM_RX_4 80
+#define QUATERNARY_TDM_TX_4 81
+#define QUATERNARY_TDM_RX_5 82
+#define QUATERNARY_TDM_TX_5 83
+#define QUATERNARY_TDM_RX_6 84
+#define QUATERNARY_TDM_TX_6 85
+#define QUATERNARY_TDM_RX_7 86
+#define QUATERNARY_TDM_TX_7 87
+#define QUINARY_TDM_RX_0 88
+#define QUINARY_TDM_TX_0 89
+#define QUINARY_TDM_RX_1 90
+#define QUINARY_TDM_TX_1 91
+#define QUINARY_TDM_RX_2 92
+#define QUINARY_TDM_TX_2 93
+#define QUINARY_TDM_RX_3 94
+#define QUINARY_TDM_TX_3 95
+#define QUINARY_TDM_RX_4 96
+#define QUINARY_TDM_TX_4 97
+#define QUINARY_TDM_RX_5 98
+#define QUINARY_TDM_TX_5 99
+#define QUINARY_TDM_RX_6 100
+#define QUINARY_TDM_TX_6 101
+#define QUINARY_TDM_RX_7 102
+#define QUINARY_TDM_TX_7 103
+#define DISPLAY_PORT_RX 104
+#define WSA_CODEC_DMA_RX_0 105
+#define WSA_CODEC_DMA_TX_0 106
+#define WSA_CODEC_DMA_RX_1 107
+#define WSA_CODEC_DMA_TX_1 108
+#define WSA_CODEC_DMA_TX_2 109
+#define VA_CODEC_DMA_TX_0 110
+#define VA_CODEC_DMA_TX_1 111
+#define VA_CODEC_DMA_TX_2 112
+#define RX_CODEC_DMA_RX_0 113
+#define TX_CODEC_DMA_TX_0 114
+#define RX_CODEC_DMA_RX_1 115
+#define TX_CODEC_DMA_TX_1 116
+#define RX_CODEC_DMA_RX_2 117
+#define TX_CODEC_DMA_TX_2 118
+#define RX_CODEC_DMA_RX_3 119
+#define TX_CODEC_DMA_TX_3 120
+#define RX_CODEC_DMA_RX_4 121
+#define TX_CODEC_DMA_TX_4 122
+#define RX_CODEC_DMA_RX_5 123
+#define TX_CODEC_DMA_TX_5 124
+#define RX_CODEC_DMA_RX_6 125
+#define RX_CODEC_DMA_RX_7 126
+
+#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
+#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
+#define LPASS_CLK_ID_SEC_MI2S_IBIT 3
+#define LPASS_CLK_ID_SEC_MI2S_EBIT 4
+#define LPASS_CLK_ID_TER_MI2S_IBIT 5
+#define LPASS_CLK_ID_TER_MI2S_EBIT 6
+#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7
+#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8
+#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9
+#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10
+#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11
+#define LPASS_CLK_ID_QUI_MI2S_IBIT 12
+#define LPASS_CLK_ID_QUI_MI2S_EBIT 13
+#define LPASS_CLK_ID_SEN_MI2S_IBIT 14
+#define LPASS_CLK_ID_SEN_MI2S_EBIT 15
+#define LPASS_CLK_ID_INT0_MI2S_IBIT 16
+#define LPASS_CLK_ID_INT1_MI2S_IBIT 17
+#define LPASS_CLK_ID_INT2_MI2S_IBIT 18
+#define LPASS_CLK_ID_INT3_MI2S_IBIT 19
+#define LPASS_CLK_ID_INT4_MI2S_IBIT 20
+#define LPASS_CLK_ID_INT5_MI2S_IBIT 21
+#define LPASS_CLK_ID_INT6_MI2S_IBIT 22
+#define LPASS_CLK_ID_QUI_MI2S_OSR 23
+#define LPASS_CLK_ID_PRI_PCM_IBIT 24
+#define LPASS_CLK_ID_PRI_PCM_EBIT 25
+#define LPASS_CLK_ID_SEC_PCM_IBIT 26
+#define LPASS_CLK_ID_SEC_PCM_EBIT 27
+#define LPASS_CLK_ID_TER_PCM_IBIT 28
+#define LPASS_CLK_ID_TER_PCM_EBIT 29
+#define LPASS_CLK_ID_QUAD_PCM_IBIT 30
+#define LPASS_CLK_ID_QUAD_PCM_EBIT 31
+#define LPASS_CLK_ID_QUIN_PCM_IBIT 32
+#define LPASS_CLK_ID_QUIN_PCM_EBIT 33
+#define LPASS_CLK_ID_QUI_PCM_OSR 34
+#define LPASS_CLK_ID_PRI_TDM_IBIT 35
+#define LPASS_CLK_ID_PRI_TDM_EBIT 36
+#define LPASS_CLK_ID_SEC_TDM_IBIT 37
+#define LPASS_CLK_ID_SEC_TDM_EBIT 38
+#define LPASS_CLK_ID_TER_TDM_IBIT 39
+#define LPASS_CLK_ID_TER_TDM_EBIT 40
+#define LPASS_CLK_ID_QUAD_TDM_IBIT 41
+#define LPASS_CLK_ID_QUAD_TDM_EBIT 42
+#define LPASS_CLK_ID_QUIN_TDM_IBIT 43
+#define LPASS_CLK_ID_QUIN_TDM_EBIT 44
+#define LPASS_CLK_ID_QUIN_TDM_OSR 45
+#define LPASS_CLK_ID_MCLK_1 46
+#define LPASS_CLK_ID_MCLK_2 47
+#define LPASS_CLK_ID_MCLK_3 48
+#define LPASS_CLK_ID_MCLK_4 49
+#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50
+#define LPASS_CLK_ID_INT_MCLK_0 51
+#define LPASS_CLK_ID_INT_MCLK_1 52
+#define LPASS_CLK_ID_MCLK_5 53
+#define LPASS_CLK_ID_WSA_CORE_MCLK 54
+#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55
+#define LPASS_CLK_ID_VA_CORE_MCLK 56
+#define LPASS_CLK_ID_TX_CORE_MCLK 57
+#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58
+#define LPASS_CLK_ID_RX_CORE_MCLK 59
+#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
+#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
+
+#define LPASS_HW_MACRO_VOTE 102
+#define LPASS_HW_DCODEC_VOTE 103
+
+#define Q6PRM_MAX_CLK_ID 104
+
+#define LPASS_CLK_ATTRIBUTE_INVALID 0x0
+#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1
+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2
+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3
+
+#endif /* __DT_BINDINGS_Q6_PRM_H__ */
@@ -109,12 +109,16 @@ config SND_SOC_QCOM_APM_DAI
config SND_SOC_QCOM_APM_BEDAI
tristate
+config SND_SOC_QCOM_PRM
+ tristate
+
config SND_SOC_QCOM_AUDIOREACH
tristate "SoC ALSA audio drives for Qualcomm AUDIOREACH"
depends on QCOM_GPR
select SND_SOC_TOPOLOGY
select SND_SOC_QCOM_APM_DAI
select SND_SOC_QCOM_APM_BEDAI
+ select SND_SOC_QCOM_PRM
help
Support for AudioReach in QDSP
@@ -2,9 +2,11 @@
snd-ar-objs := audioreach.o q6apm.o topology.o
snd-apm-dai-objs := q6apm-dai.o
snd-apm-bedai-objs := q6apm-bedai.o
+snd-prm-objs := q6prm.o
obj-$(CONFIG_SND_SOC_QCOM_AUDIOREACH) += snd-ar.o
obj-$(CONFIG_SND_SOC_QCOM_APM_DAI) += snd-apm-dai.o
obj-$(CONFIG_SND_SOC_QCOM_APM_BEDAI) += snd-apm-bedai.o
+obj-$(CONFIG_SND_SOC_QCOM_PRM) += snd-prm.o
new file mode 100644
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021, Linaro Limited
+
+#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/delay.h>
+#include <linux/of_platform.h>
+#include <linux/clk-provider.h>
+#include <linux/jiffies.h>
+#include <linux/soc/qcom/gpr.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/sound/qcom,q6prm.h>
+#include "audioreach.h"
+
+#define Q6PRM_CLK(id) &(struct q6prm_clk) { \
+ .clk_id = id, \
+ .afe_clk_id = Q6PRM_##id, \
+ .name = #id, \
+ .attributes = LPASS_CLK_ATTRIBUTE_COUPLE_NO, \
+ .rate = 19200000, \
+ .hw.init = &(struct clk_init_data) { \
+ .ops = &clk_q6prm_ops, \
+ .name = #id, \
+ }, \
+ }
+
+#define Q6PRM_VOTE_CLK(id, blkid) &(struct q6prm_clk) { \
+ .clk_id = id, \
+ .afe_clk_id = blkid, \
+ .hw.init = &(struct clk_init_data) { \
+ .ops = &clk_vote_q6prm_ops, \
+ .name = #id, \
+ }, \
+ }
+
+struct q6prm_clk {
+ struct device *dev;
+ int clk_id;
+ int afe_clk_id;
+ char *name;
+ int attributes;
+ int rate;
+ uint32_t handle;
+ struct clk_hw hw;
+};
+#define to_q6prm_clk(_hw) container_of(_hw, struct q6prm_clk, hw)
+
+struct q6prm {
+ struct device *dev;
+ struct gpr_device *gdev;
+ wait_queue_head_t wait;
+ struct gpr_ibasic_rsp_result_t result;
+ struct mutex lock;
+ struct q6prm_clk **clks;
+ int num_clks;
+};
+
+#define PRM_CMD_REQUEST_HW_RSC 0x0100100F
+#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002
+#define PRM_CMD_RELEASE_HW_RSC 0x01001010
+#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003
+
+#define PARAM_ID_RSC_HW_CORE 0x08001032
+#define PARAM_ID_RSC_LPASS_CORE 0x0800102B
+#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C
+
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
+#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
+
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307
+#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308
+
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
+#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
+
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
+#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
+
+#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
+#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
+#define Q6PRM_HW_CORE_ID_LPASS 1
+#define Q6PRM_HW_CORE_ID_DCODEC 2
+
+struct prm_cmd_request_hw_core {
+ struct apm_module_param_data param_data;
+ uint32_t hw_clk_id;
+} __packed;
+
+struct prm_cmd_request_rsc {
+ struct apm_module_param_data param_data;
+ uint32_t num_clk_id;
+ struct audio_hw_clk_cfg clock_ids[1];
+} __packed;
+
+struct prm_cmd_release_rsc {
+ struct apm_module_param_data param_data;
+ uint32_t num_clk_id;
+ struct audio_hw_clk_cfg clock_ids[1];
+} __packed;
+
+static int q6prm_send_cmd_sync(struct q6prm *prm, struct gpr_pkt *pkt,
+ uint32_t rsp_opcode)
+{
+ struct gpr_device *gdev = prm->gdev;
+ struct gpr_hdr *hdr = &pkt->hdr;
+ int rc;
+
+ mutex_lock(&prm->lock);
+ prm->result.opcode = 0;
+ prm->result.status = 0;
+
+ rc = gpr_send_pkt(prm->gdev, pkt);
+ if (rc < 0)
+ goto err;
+
+ if (rsp_opcode)
+ rc = wait_event_timeout(prm->wait,
+ (prm->result.opcode == hdr->opcode) ||
+ (prm->result.opcode == rsp_opcode),
+ 5 * HZ);
+ else
+ rc = wait_event_timeout(prm->wait,
+ (prm->result.opcode == hdr->opcode),
+ 5 * HZ);
+
+ if (!rc) {
+ dev_err(&gdev->dev, "CMD timeout for [%x] opcode\n",
+ hdr->opcode);
+ rc = -ETIMEDOUT;
+ } else if (prm->result.status > 0) {
+ dev_err(&gdev->dev, "DSP returned error[%x] %x\n", hdr->opcode,
+ prm->result.status);
+ rc = -EINVAL;
+ } else {
+ dev_err(&gdev->dev, "DSP returned [%x]\n",
+ prm->result.status);
+ rc = 0;
+ }
+
+err:
+ mutex_unlock(&prm->lock);
+ return rc;
+}
+
+static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable)
+{
+ struct prm_cmd_request_hw_core *req;
+ struct apm_module_param_data *param_data;
+ struct gpr_pkt *pkt;
+ struct q6prm *prm = dev_get_drvdata(dev);
+ struct gpr_device *gdev = prm->gdev;
+ void *p;
+ int rc = 0;
+ uint32_t opcode, rsp_opcode;
+
+ if (enable) {
+ opcode = PRM_CMD_REQUEST_HW_RSC;
+ rsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC;
+ } else {
+ opcode = PRM_CMD_RELEASE_HW_RSC;
+ rsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC;
+ }
+
+ p = audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->port.id,
+ GPR_PRM_MODULE_IID);
+ if (IS_ERR(p))
+ return -ENOMEM;
+
+ pkt = p;
+ req = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
+
+ param_data = &req->param_data;
+
+ param_data->module_instance_id = GPR_PRM_MODULE_IID;
+ param_data->error_code = 0;
+ param_data->param_id = PARAM_ID_RSC_HW_CORE;
+ param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
+
+ req->hw_clk_id = hw_block_id;
+
+ q6prm_send_cmd_sync(prm, pkt, rsp_opcode);
+
+ kfree(pkt);
+
+ return rc;
+}
+
+static int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr,
+ int clk_root, unsigned int freq)
+{
+ struct prm_cmd_request_rsc *req;
+ struct apm_module_param_data *param_data;
+ struct gpr_pkt *pkt;
+ struct q6prm *prm = dev_get_drvdata(dev);
+ struct gpr_device *gdev = prm->gdev;
+ void *p;
+ int rc = 0;
+
+ p = audioreach_alloc_cmd_pkt(sizeof(*req), PRM_CMD_REQUEST_HW_RSC,
+ 0, gdev->port.id, GPR_PRM_MODULE_IID);
+ if (IS_ERR(p))
+ return -ENOMEM;
+
+ pkt = p;
+ req = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE;
+
+ param_data = &req->param_data;
+
+ param_data->module_instance_id = GPR_PRM_MODULE_IID;
+ param_data->error_code = 0;
+ param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK;
+ param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE;
+
+ req->num_clk_id = 1;
+ req->clock_ids[0].clock_id = clk_id;
+ req->clock_ids[0].clock_freq = freq;
+ req->clock_ids[0].clock_attri = clk_attr;
+ req->clock_ids[0].clock_root = clk_root;
+
+ q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_REQUEST_HW_RSC);
+
+ kfree(pkt);
+
+ return rc;
+}
+
+static int prm_callback(struct gpr_resp_pkt *data, void *priv, int op)
+{
+ struct gpr_device *gdev = priv;
+ struct q6prm *prm = dev_get_drvdata(&gdev->dev);
+ struct gpr_ibasic_rsp_result_t *result;
+ struct gpr_hdr *hdr = &data->hdr;
+
+ result = data->payload;
+
+ switch (hdr->opcode) {
+ case PRM_CMD_RSP_REQUEST_HW_RSC:
+ case PRM_CMD_RSP_RELEASE_HW_RSC:
+ prm->result.opcode = hdr->opcode;
+ prm->result.status = result->status;
+ wake_up(&prm->wait);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int clk_q6prm_prepare(struct clk_hw *hw)
+{
+ struct q6prm_clk *clk = to_q6prm_clk(hw);
+
+ return q6prm_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
+ Q6PRM_LPASS_CLK_ROOT_DEFAULT, clk->rate);
+}
+
+static void clk_q6prm_unprepare(struct clk_hw *hw)
+{
+ struct q6prm_clk *clk = to_q6prm_clk(hw);
+
+ q6prm_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes,
+ Q6PRM_LPASS_CLK_ROOT_DEFAULT, 0);
+}
+
+static int clk_q6prm_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct q6prm_clk *clk = to_q6prm_clk(hw);
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+static unsigned long clk_q6prm_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct q6prm_clk *clk = to_q6prm_clk(hw);
+
+ return clk->rate;
+}
+
+static long clk_q6prm_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return rate;
+}
+
+static const struct clk_ops clk_q6prm_ops = {
+ .prepare = clk_q6prm_prepare,
+ .unprepare = clk_q6prm_unprepare,
+ .set_rate = clk_q6prm_set_rate,
+ .round_rate = clk_q6prm_round_rate,
+ .recalc_rate = clk_q6prm_recalc_rate,
+};
+
+static int clk_vote_q6prm_block(struct clk_hw *hw)
+{
+ struct q6prm_clk *clk = to_q6prm_clk(hw);
+
+ return q6prm_set_hw_core_req(clk->dev, clk->afe_clk_id, true);
+}
+
+static void clk_unvote_q6prm_block(struct clk_hw *hw)
+{
+ struct q6prm_clk *clk = to_q6prm_clk(hw);
+
+ q6prm_set_hw_core_req(clk->dev, clk->afe_clk_id, false);
+}
+
+static const struct clk_ops clk_vote_q6prm_ops = {
+ .prepare = clk_vote_q6prm_block,
+ .unprepare = clk_unvote_q6prm_block,
+};
+
+static struct q6prm_clk *q6prm_clks[Q6PRM_MAX_CLK_ID] = {
+ [LPASS_CLK_ID_WSA_CORE_MCLK] = Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
+ [LPASS_CLK_ID_WSA_CORE_NPL_MCLK] =
+ Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
+ [LPASS_CLK_ID_VA_CORE_MCLK] = Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
+ [LPASS_CLK_ID_TX_CORE_MCLK] = Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
+ [LPASS_CLK_ID_TX_CORE_NPL_MCLK] =
+ Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
+ [LPASS_CLK_ID_RX_CORE_MCLK] = Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
+ [LPASS_CLK_ID_RX_CORE_NPL_MCLK] =
+ Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
+ [LPASS_CLK_ID_VA_CORE_2X_MCLK] =
+ Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
+ [LPASS_HW_MACRO_VOTE] = Q6PRM_VOTE_CLK(LPASS_HW_MACRO_VOTE,
+ Q6PRM_HW_CORE_ID_LPASS),
+ [LPASS_HW_DCODEC_VOTE] = Q6PRM_VOTE_CLK(LPASS_HW_DCODEC_VOTE,
+ Q6PRM_HW_CORE_ID_DCODEC),
+};
+
+static struct clk_hw *q6prm_of_clk_hw_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ struct q6prm *cc = data;
+ unsigned int idx = clkspec->args[0];
+ unsigned int attr = clkspec->args[1];
+
+ if (idx >= cc->num_clks || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) {
+ dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr);
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (cc->clks[idx]) {
+ cc->clks[idx]->attributes = attr;
+ return &cc->clks[idx]->hw;
+ }
+
+ return ERR_PTR(-ENOENT);
+}
+
+static int prm_probe(struct gpr_device *gdev)
+{
+ struct device *dev = &gdev->dev;
+ struct q6prm *cc;
+ int i, ret;
+
+ cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
+ if (!cc)
+ return -ENOMEM;
+
+ cc->dev = dev;
+ cc->gdev = gdev;
+ mutex_init(&cc->lock);
+ init_waitqueue_head(&cc->wait);
+ cc->clks = &q6prm_clks[0];
+ cc->num_clks = ARRAY_SIZE(q6prm_clks);
+ for (i = 0; i < ARRAY_SIZE(q6prm_clks); i++) {
+ if (!q6prm_clks[i])
+ continue;
+
+ q6prm_clks[i]->dev = dev;
+
+ ret = devm_clk_hw_register(dev, &q6prm_clks[i]->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = of_clk_add_hw_provider(dev->of_node, q6prm_of_clk_hw_get, cc);
+ if (ret)
+ return ret;
+
+ dev_set_drvdata(dev, cc);
+
+ return 0;
+}
+
+static const struct of_device_id prm_device_id[] = {
+ { .compatible = "qcom,q6prm" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, prm_device_id);
+
+static struct gpr_driver prm_driver = {
+ .probe = prm_probe,
+ .callback = prm_callback,
+ .driver = {
+ .name = "qcom-prm",
+ .of_match_table = of_match_ptr(prm_device_id),
+ },
+};
+
+module_gpr_driver(prm_driver);
+MODULE_DESCRIPTION("Audio Process Manager");
+MODULE_LICENSE("GPL v2");
Add support to q6prm (Proxy Resource Manager) module used for clock resources Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- include/dt-bindings/sound/qcom,q6prm.h | 205 ++++++++++++ sound/soc/qcom/Kconfig | 4 + sound/soc/qcom/audioreach/Makefile | 2 + sound/soc/qcom/audioreach/q6prm.c | 412 +++++++++++++++++++++++++ 4 files changed, 623 insertions(+) create mode 100644 include/dt-bindings/sound/qcom,q6prm.h create mode 100644 sound/soc/qcom/audioreach/q6prm.c -- 2.21.0