Message ID | 20210601090408.22025-5-qiangqing.zhang@nxp.com |
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State | New |
Headers | show
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Tue, 1 Jun 2021 09:04:54 +0000 From: Joakim Zhang <qiangqing.zhang@nxp.com> To: davem@davemloft.net, kuba@kernel.org, robh+dt@kernel.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, f.fainelli@gmail.com Cc: linux-imx@nxp.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 4/4] net: phy: realtek: add delay to fix RXC generation issue Date: Tue, 1 Jun 2021 17:04:08 +0800 Message-Id: <20210601090408.22025-5-qiangqing.zhang@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210601090408.22025-1-qiangqing.zhang@nxp.com> References: <20210601090408.22025-1-qiangqing.zhang@nxp.com> Content-Type: text/plain X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SGBP274CA0013.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b0::25) To DB8PR04MB6795.eurprd04.prod.outlook.com (2603:10a6:10:fa::15) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.71) by SGBP274CA0013.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b0::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.20 via Frontend Transport; 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net: phy: add dt property for realtek phy
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expand
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diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 90e3a8cbfc2f..b45deda839f8 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -408,6 +408,22 @@ static int rtl8211f_config_init(struct phy_device *phydev) return genphy_soft_reset(phydev); } +static int rtl821x_resume(struct phy_device *phydev) +{ + struct rtl821x_priv *priv = phydev->priv; + int ret; + + ret = genphy_resume(phydev); + if (ret < 0) + return ret; + + /* delay time is collected with ALDPS mode disabled. */ + if (priv->quirks & RTL821X_ALDPS_DISABLE_FEATURE) + msleep(20); + + return 0; +} + static int rtl8211e_config_init(struct phy_device *phydev) { int ret = 0, oldpage; @@ -904,7 +920,7 @@ static struct phy_driver realtek_drvs[] = { .config_intr = &rtl8211f_config_intr, .handle_interrupt = rtl8211f_handle_interrupt, .suspend = genphy_suspend, - .resume = genphy_resume, + .resume = rtl821x_resume, .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, }, {
PHY will delay about 11.5ms to generate RXC clock when switching from power down to normal operation. Read/write registers would also cause RXC become unstable and stop for a while during this process. Realtek engineer suggests 15ms or more delay can workaround this issue. All these statistics are collected with ALDPS mode disabled, so use RTL821X_ALDPS_DISABLE quirk check. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> --- drivers/net/phy/realtek.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)