diff mbox series

[1/1] arm64: dts: apm: Separate each group of data in the property 'reg'

Message ID 20210521085705.8312-1-thunder.leizhen@huawei.com
State New
Headers show
Series [1/1] arm64: dts: apm: Separate each group of data in the property 'reg' | expand

Commit Message

Leizhen (ThunderTown) May 21, 2021, 8:57 a.m. UTC 
Do not write the 'reg' of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.

arch/arm64/boot/dts/apm/apm-merlin.dt.yaml:
soc: pcie@1f2c0000:reg:0: \
[0, 522977280, 0, 65536, 160, 3489660928, 0, 262144] is too long

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>

---
 arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 12 +++++------
 arch/arm64/boot/dts/apm/apm-storm.dtsi     | 24 +++++++++++-----------
 2 files changed, 18 insertions(+), 18 deletions(-)

-- 
2.26.0.106.g9fadedd
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index a83c82c50e29912..1c7fa5ca92ac68b 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -320,8 +320,8 @@  sdioclk: sdioclk@1f2ac000 {
 				compatible = "apm,xgene-device-clock";
 				#clock-cells = <1>;
 				clocks = <&socplldiv2 0>;
-				reg = <0x0 0x1f2ac000 0x0 0x1000
-					0x0 0x17000000 0x0 0x2000>;
+				reg = <0x0 0x1f2ac000 0x0 0x1000>,
+				      <0x0 0x17000000 0x0 0x2000>;
 				reg-names = "csr-reg", "div-reg";
 				csr-offset = <0x0>;
 				csr-mask = <0x2>;
@@ -614,8 +614,8 @@  pcie0: pcie@1f2b0000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
-				0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+			reg = <0x00 0x1f2b0000 0x0 0x00010000>,  /* Controller registers */
+			      <0xc0 0xd0000000 0x0 0x00040000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io */
 				  0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000   /* mem */
@@ -640,8 +640,8 @@  pcie1: pcie@1f2c0000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
-				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+			reg = <0x00 0x1f2c0000 0x0 0x00010000>,  /* Controller registers */
+			      <0xa0 0xd0000000 0x0 0x00040000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io */
 				  0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000   /* mem */
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 0f37e77f5459951..5841355f07d78a2 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -182,8 +182,8 @@  sdioclk: sdioclk@1f2ac000 {
 				compatible = "apm,xgene-device-clock";
 				#clock-cells = <1>;
 				clocks = <&socplldiv2 0>;
-				reg = <0x0 0x1f2ac000 0x0 0x1000
-					0x0 0x17000000 0x0 0x2000>;
+				reg = <0x0 0x1f2ac000 0x0 0x1000>,
+				      <0x0 0x17000000 0x0 0x2000>;
 				reg-names = "csr-reg", "div-reg";
 				csr-offset = <0x0>;
 				csr-mask = <0x2>;
@@ -614,8 +614,8 @@  pcie0: pcie@1f2b0000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
-				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+			reg = <0x00 0x1f2b0000 0x0 0x00010000>,  /* Controller registers */
+			      <0xe0 0xd0000000 0x0 0x00040000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
@@ -640,8 +640,8 @@  pcie1: pcie@1f2c0000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
-				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+			reg = <0x00 0x1f2c0000 0x0 0x00010000>,  /* Controller registers */
+			      <0xd0 0xd0000000 0x0 0x00040000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
@@ -666,8 +666,8 @@  pcie2: pcie@1f2d0000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
-				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
+			reg =  <0x00 0x1f2d0000 0x0 0x00010000>,  /* Controller registers */
+			       <0x90 0xd0000000 0x0 0x00040000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
@@ -692,8 +692,8 @@  pcie3: pcie@1f500000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
-				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+			reg = <0x00 0x1f500000 0x0 0x00010000>,  /* Controller registers */
+			      <0xa0 0xd0000000 0x0 0x00040000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
@@ -718,8 +718,8 @@  pcie4: pcie@1f510000 {
 			#interrupt-cells = <1>;
 			#size-cells = <2>;
 			#address-cells = <3>;
-			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
-				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
+			reg = <0x00 0x1f510000 0x0 0x00010000>,  /* Controller registers */
+			      <0xc0 0xd0000000 0x0 0x00200000>;  /* PCI config space */
 			reg-names = "csr", "cfg";
 			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */