| Message ID | 1620990152-19255-4-git-send-email-dillon.minfei@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
Hi Dillon On 5/14/21 1:02 PM, dillon.minfei@gmail.com wrote: > From: Dillon Min <dillon.minfei@gmail.com> > > This is due to misuse ‘PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c > 'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in > include/dt-bindings/clock/stm32fx-clock.h). > > 'post_div' point to 'post_div_data[]', 'post_div->pll_num' > is PLL_I2S or PLL_SAI. > > 'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return > from stm32f4_rcc_register_pll() but, at line 1777 of > driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]', > equal to 'clks[PLL_SAI]', this is invalid array member at that time. > > Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs") > Signed-off-by: Dillon Min <dillon.minfei@gmail.com> > Acked-by: Stephen Boyd <sboyd@kernel.org> > Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-6-git-send-email-dillon.minfei@gmail.com/ > --- > drivers/clk/clk-stm32f4.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c > index 18117ce5ff85..42ca2dd86aea 100644 > --- a/drivers/clk/clk-stm32f4.c > +++ b/drivers/clk/clk-stm32f4.c > @@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = { > > #define MAX_POST_DIV 3 > static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { > - { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q", > + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", > CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, > > - { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q", > + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", > CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, > > - { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, > + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, > STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, > }; > > Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Thanks Patrice
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 18117ce5ff85..42ca2dd86aea 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = { #define MAX_POST_DIV 3 static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { - { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q", + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, - { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q", + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, - { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, };