@@ -84,6 +84,22 @@ properties:
minimum: 0x0
maximum: 0x7
+ lantiq,phy3:
+ description:
+ The gphy3 core can control 3 bits of the gpio cascade. Available on
+ the xRX300 and xRX330 family.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x0
+ maximum: 0x7
+
+ lantiq,phy4:
+ description:
+ The gphy4 core can control 3 bits of the gpio cascade. Available on
+ the xRX330 family.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x0
+ maximum: 0x7
+
lantiq,rising:
description:
Use rising instead of falling edge for the shift register.
The xRX300 family has 3 and the xRX330 has 4 gphs. They can also control some pins of the gpio cascade. This patch documents the missing properties. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> --- .../devicetree/bindings/gpio/gpio-stp-xway.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)