| Message ID | 20210510185931.104780-1-l.stach@pengutronix.de |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/3] arm64: dts: imx8mq: add Nitrogen8 SoM | expand |
Hi Lucas, On Mon, May 10, 2021 at 4:00 PM Lucas Stach <l.stach@pengutronix.de> wrote: > > From: Lucas Stach <dev@lynxeye.de> > > This adds the description of the Nitrogen8 System on Module. The module > is quite simple with only a few (almost) fixed regulators and a eMMC > on-board. > > The eMMC is currently limited to 50MHz modes via the pinctrl, as the board > has not wired up the data strobe line, which prevents HS400 mode from > working. As both the controller and the eMMC support this mode, it is > automatically selected when we allow the faster modes, leading to failing > transfers. Until we have a proper solution to only disable HS400 mode, > keep the eMMC at the slow bus modes. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
On Mon, May 10, 2021 at 4:00 PM Lucas Stach <l.stach@pengutronix.de> wrote: > +&i2c3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; > + > + pcf8523: pcf8523@68 { Just a nit: node names should be generic: rtc@68 Reviewed-by: Fabio Estevam <festevam@gmail.com>
On Mon, 10 May 2021 20:59:29 +0200, Lucas Stach wrote: > From: Lucas Stach <dev@lynxeye.de> > > This adds the description of the Nitrogen8 System on Module. The module > is quite simple with only a few (almost) fixed regulators and a eMMC > on-board. > > The eMMC is currently limited to 50MHz modes via the pinctrl, as the board > has not wired up the data strobe line, which prevents HS400 mode from > working. As both the controller and the eMMC support this mode, it is > automatically selected when we allow the faster modes, leading to failing > transfers. Until we have a proper solution to only disable HS400 mode, > keep the eMMC at the slow bus modes. > > Signed-off-by: Lucas Stach <dev@lynxeye.de> > --- > v2: > - remove 100/200MHz pinctrl states for usdhc1 > - rename i2c nodes > --- > .../devicetree/bindings/arm/fsl.yaml | 1 + > .../dts/freescale/imx8mq-nitrogen-som.dtsi | 242 ++++++++++++++++++ > 2 files changed, 243 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi > Reviewed-by: Rob Herring <robh@kernel.org>
On Mon, 10 May 2021 20:59:31 +0200, Lucas Stach wrote: > From: Lucas Stach <dev@lynxeye.de> > > This adds a basic devicetree for the MNT Reform2 DIY laptop. Not all > of the board periperals are enabled yet, as some of them still require > kernel patches to work properly. The nodes for those peripherals will > be added as soon as the required patches are upstream. > > The following has been tested to work: > - UART console > - SD card > - eMMC > - Gigabit Ethernet > - USB (internal Keyboard, Mouse, external ports) > - M.2 PCIe port > > Co-developed-by: Lukas F. Hartmann <lukas@mntre.com> > Signed-off-by: Lucas Stach <dev@lynxeye.de> > --- > v2: Fix checkpatch complaints. > --- > .../devicetree/bindings/arm/fsl.yaml | 1 + > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx8mq-mnt-reform2.dts | 164 ++++++++++++++++++ > 3 files changed, 166 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts > Reviewed-by: Rob Herring <robh@kernel.org>
On Mon, May 10, 2021 at 08:59:31PM +0200, Lucas Stach wrote: > From: Lucas Stach <dev@lynxeye.de> > > This adds a basic devicetree for the MNT Reform2 DIY laptop. Not all > of the board periperals are enabled yet, as some of them still require > kernel patches to work properly. The nodes for those peripherals will > be added as soon as the required patches are upstream. > > The following has been tested to work: > - UART console > - SD card > - eMMC > - Gigabit Ethernet > - USB (internal Keyboard, Mouse, external ports) > - M.2 PCIe port > > Co-developed-by: Lukas F. Hartmann <lukas@mntre.com> > Signed-off-by: Lucas Stach <dev@lynxeye.de> > --- > v2: Fix checkpatch complaints. > --- > .../devicetree/bindings/arm/fsl.yaml | 1 + Bindings goes to separate patch. > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx8mq-mnt-reform2.dts | 164 ++++++++++++++++++ > 3 files changed, 166 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml > index 15519cc2d2c0..fd208c7e49ae 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.yaml > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml > @@ -737,6 +737,7 @@ properties: > - purism,librem5-devkit # Purism Librem5 devkit > - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse > - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk > + - mntre,reform2 # MNT Reform2 Laptop Break order. > - const: fsl,imx8mq > > - description: Purism Librem5 phones > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 44890d56c194..e45c8f9c8912 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -54,6 +54,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r4.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mq-mnt-reform2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-phanbell.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts > new file mode 100644 > index 000000000000..104a236c9609 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts > @@ -0,0 +1,164 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +/* > + * Copyright 2019-2021 MNT Research GmbH > + * Copyright 2021 Lucas Stach <dev@lynxeye.de> > + */ > + > +/dts-v1/; > + > +#include "imx8mq-nitrogen-som.dtsi" > + > +/ { > + model = "MNT Reform 2"; > + compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; > + > + pcie1_refclk: clock-pcie1-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > + > + reg_main_5v: regulator-main-5v { > + compatible = "regulator-fixed"; > + regulator-name = "5V"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > + > + reg_main_3v3: regulator-main-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + reg_main_usb: regulator-main-usb { > + compatible = "regulator-fixed"; > + regulator-name = "USB_PWR"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + vin-supply = <®_main_5v>; > + }; > +}; > + > +&fec1 { > + status = "okay"; > +}; > + > +&i2c3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; > + > + pcf8523: pcf8523@68 { > + compatible = "nxp,pcf8523"; > + reg = <0x68>; > + }; > +}; > + > +&pcie1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie1>; > + reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, > + <&clk IMX8MQ_CLK_PCIE2_AUX>, > + <&clk IMX8MQ_CLK_PCIE2_PHY>, > + <&pcie1_refclk>; > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; > + status = "okay"; > +}; > + > +®_1p8v { > + vin-supply = <®_main_5v>; > +}; > + > +®_snvs { > + vin-supply = <®_main_5v>; > +}; > + > +®_arm_dram { > + vin-supply = <®_main_5v>; > +}; > + > +®_dram_1p1v { > + vin-supply = <®_main_5v>; > +}; > + > +®_soc_gpu_vpu { > + vin-supply = <®_main_5v>; > +}; > + > +&snvs_rtc { > + status = "disabled"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + status = "okay"; > +}; > + > +&usb3_phy0 { > + vbus-supply = <®_main_usb>; > + status = "okay"; > +}; > + > +&usb3_phy1 { > + vbus-supply = <®_main_usb>; > + status = "okay"; > +}; > + > +&usb_dwc3_0 { > + status = "okay"; > + dr_mode = "host"; End property list with 'status' please. > +}; > + > +&usb_dwc3_1 { > + status = "okay"; > + dr_mode = "host"; Ditto Shawn > +}; > + > +&usdhc2 { > + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; > + assigned-clock-rates = <200000000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + vqmmc-supply = <®_main_3v3>; > + vmmc-supply = <®_main_3v3>; > + bus-width = <4>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f > + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f > + >; > + }; > + > + pinctrl_pcie1: pcie1grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 > + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 > + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 > + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 > + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 > + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 > + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 > + >; > + }; > +}; > -- > 2.31.1 >
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 297c87f45db8..15519cc2d2c0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -730,6 +730,7 @@ properties: items: - enum: - boundary,imx8mq-nitrogen8m # i.MX8MQ NITROGEN Board + - boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM - einfochips,imx8mq-thor96 # i.MX8MQ Thor96 Board - fsl,imx8mq-evk # i.MX8MQ EVK Board - google,imx8mq-phanbell # Google Coral Edge TPU diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi new file mode 100644 index 000000000000..7f20d9b9ffb3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen-som.dtsi @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Boundary Devices + * Copyright 2021 Lucas Stach <dev@lynxeye.de> + */ + +#include "imx8mq.dtsi" + +/ { + model = "Boundary Devices i.MX8MQ Nitrogen8M"; + compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + reg_1p8v: regulator-fixed-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_snvs: regulator-fixed-snvs { + compatible = "regulator-fixed"; + regulator-name = "VDD_SNVS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&{/opp-table/opp-800000000} { + opp-microvolt = <1000000>; +}; + +&{/opp-table/opp-1000000000} { + opp-microvolt = <1000000>; +}; + +&A53_0 { + cpu-supply = <®_arm_dram>; +}; + +&A53_1 { + cpu-supply = <®_arm_dram>; +}; + +&A53_2 { + cpu-supply = <®_arm_dram>; +}; + +&A53_3 { + cpu-supply = <®_arm_dram>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_pca9546>; + reg = <0x70>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c1a: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + reg_arm_dram: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "VDD_ARM_DRAM_1V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + + i2c1b: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + reg_dram_1p1v: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "NVCC_DRAM_1P1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + }; + + i2c1c: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + reg_soc_gpu_vpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "VDD_SOC_GPU_VPU"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + }; + + i2c1d: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&pgc_gpu { + power-supply = <®_soc_gpu_vpu>; +}; + +&pgc_vpu { + power-supply = <®_soc_gpu_vpu>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_snvs>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_pca9546: i2c1-pca9546grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +};