| Message ID | 20210427073733.31419-1-jon.lin@rock-chips.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2,1/8] spi: rockchip: Set rx_fifo interrupt waterline base on transfer item | expand |
Hi Jon Lin, On Tue, Apr 27, 2021 at 03:37:27PM +0800, Jon Lin wrote: > +static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode) > { > unsigned long timeout = jiffies + msecs_to_jiffies(5); > > do { > - if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) > - return; > + if (slave_mode) { > + if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) && > + !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) > + return; This doesn't compile. There is one opening brace too much before the readl_relaxed. Regards, Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 52d6259d96ed..406ea3c6abd9 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -540,8 +540,8 @@ static int rockchip_spi_config(struct rockchip_spi *rs, * interrupt exactly when the fifo is full doesn't seem to work, * so we need the strict inequality here */ - if (xfer->len < rs->fifo_len) - writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); + if ((xfer->len / rs->n_bytes) < rs->fifo_len) + writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); else writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
The error here is to calculate the width as 8 bits. In fact, 16 bits should be considered. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> --- drivers/spi/spi-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)