@@ -86,10 +86,6 @@ &de {
status = "okay";
};
-&dwc3 {
- status = "okay";
-};
-
&ehci0 {
status = "okay";
};
@@ -333,6 +329,6 @@ &usb2phy {
status = "okay";
};
-&usb3phy {
+&usb3 {
status = "okay";
};
@@ -111,10 +111,6 @@ &de {
status = "okay";
};
-&dwc3 {
- status = "okay";
-};
-
&ehci0 {
status = "okay";
};
@@ -388,6 +384,6 @@ &usb2phy {
status = "okay";
};
-&usb3phy {
+&usb3 {
status = "okay";
};
@@ -94,10 +94,6 @@ &de {
status = "okay";
};
-&dwc3 {
- status = "okay";
-};
-
&ehci0 {
status = "okay";
};
@@ -362,7 +358,10 @@ &usb2phy {
status = "okay";
};
+&usb3 {
+ status = "okay";
+};
+
&usb3phy {
phy-supply = <®_usb_vbus>;
- status = "okay";
};
@@ -55,10 +55,6 @@ &de {
status = "okay";
};
-&dwc3 {
- status = "okay";
-};
-
&ehci0 {
status = "okay";
};
@@ -119,6 +115,6 @@ &usb2phy {
status = "okay";
};
-&usb3phy {
+&usb3 {
status = "okay";
};
@@ -797,36 +797,42 @@ ohci0: usb@5101400 {
status = "disabled";
};
- dwc3: usb@5200000 {
- compatible = "snps,dwc3";
- reg = <0x05200000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_XHCI>,
- <&ccu CLK_BUS_XHCI>,
- <&rtc 0>;
- clock-names = "ref", "bus_early", "suspend";
+ usb3: usb@5200000 {
+ compatible = "allwinner,sun50i-h6-dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
resets = <&ccu RST_BUS_XHCI>;
- /*
- * The datasheet of the chip doesn't declare the
- * peripheral function, and there's no boards known
- * to have a USB Type-B port routed to the port.
- * In addition, no one has tested the peripheral
- * function yet.
- * So set the dr_mode to "host" in the DTSI file.
- */
- dr_mode = "host";
- phys = <&usb3phy>;
- phy-names = "usb3-phy";
status = "disabled";
- };
- usb3phy: phy@5210000 {
- compatible = "allwinner,sun50i-h6-usb3-phy";
- reg = <0x5210000 0x10000>;
- clocks = <&ccu CLK_USB_PHY1>;
- resets = <&ccu RST_USB_PHY1>;
- #phy-cells = <0>;
- status = "disabled";
+ dwc3: usb@5200000 {
+ compatible = "snps,dwc3";
+ reg = <0x05200000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_XHCI>,
+ <&ccu CLK_BUS_XHCI>,
+ <&rtc 0>;
+ clock-names = "ref", "bus_early", "suspend";
+ /*
+ * The datasheet of the chip doesn't declare the
+ * peripheral function, and there's no boards known
+ * to have a USB Type-B port routed to the port.
+ * In addition, no one has tested the peripheral
+ * function yet.
+ * So set the dr_mode to "host" in the DTSI file.
+ */
+ dr_mode = "host";
+ phys = <&usb3phy>;
+ phy-names = "usb3-phy";
+ };
+
+ usb3phy: phy@5210000 {
+ compatible = "allwinner,sun50i-h6-usb3-phy";
+ reg = <0x5210000 0x10000>;
+ clocks = <&ccu CLK_USB_PHY1>;
+ resets = <&ccu RST_USB_PHY1>;
+ #phy-cells = <0>;
+ };
};
ehci3: usb@5311000 {
The USB3 IP in the H6 is organized such that the reset line affects both the DWC3 core and the PHY. To model that, following the example of several other platforms, wrap those nodes in a glue layer node. The inner nodes no longer need to be disabled, since the glue layer is disabled by default to keep it in reset. Signed-off-by: Samuel Holland <samuel@sholland.org> --- .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 +- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 6 +- .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 ++- .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 6 +- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 ++++++++++--------- 5 files changed, 40 insertions(+), 47 deletions(-)