| Message ID | 20210416235928.1631788-6-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement BFloat16 | expand |
On Sat, 17 Apr 2021 at 01:02, Richard Henderson <richard.henderson@linaro.org> wrote: > > For Arm BFDOT and BFMMLA, we need a version of round-to-odd > that overflows to infinity, instead of the max normal number. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > include/fpu/softfloat-types.h | 4 +++- > fpu/softfloat.c | 8 ++++++-- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h > index 8a3f20fae9..3b757c3d6a 100644 > --- a/include/fpu/softfloat-types.h > +++ b/include/fpu/softfloat-types.h > @@ -134,8 +134,10 @@ typedef enum __attribute__((__packed__)) { > float_round_up = 2, > float_round_to_zero = 3, > float_round_ties_away = 4, > - /* Not an IEEE rounding mode: round to the closest odd mantissa value */ > + /* Not an IEEE rounding mode: round to closest odd, overflow to max */ > float_round_to_odd = 5, > + /* Not an IEEE rounding mode: round to closest odd, overflow to inf */ > + float_round_to_odd_inf = 6, > } FloatRoundMode; > > /* > diff --git a/fpu/softfloat.c b/fpu/softfloat.c > index 67cfa0fd82..76097679b0 100644 > --- a/fpu/softfloat.c > +++ b/fpu/softfloat.c > @@ -694,13 +694,12 @@ static FloatParts round_canonical(FloatParts p, float_status *s, > > switch (p.cls) { > case float_class_normal: > + overflow_norm = false; > switch (s->float_rounding_mode) { > case float_round_nearest_even: > - overflow_norm = false; > inc = ((frac & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0); > break; > case float_round_ties_away: > - overflow_norm = false; > inc = frac_lsbm1; > break; > case float_round_to_zero: > @@ -717,6 +716,8 @@ static FloatParts round_canonical(FloatParts p, float_status *s, > break; > case float_round_to_odd: > overflow_norm = true; > + /* fall through */ > + case float_round_to_odd_inf: > inc = frac & frac_lsb ? 0 : round_mask; > break; > default: > @@ -771,6 +772,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s, > ? frac_lsbm1 : 0); > break; > case float_round_to_odd: > + case float_round_to_odd_inf: > inc = frac & frac_lsb ? 0 : round_mask; > break; > default: > @@ -6860,6 +6862,8 @@ float128 float128_round_to_int(float128 a, float_status *status) > > case float_round_to_zero: > break; > + default: > + g_assert_not_reached(); > } > return packFloat128( aSign, 0, 0, 0 ); > } This code change looks OK as far as it goes, but there are a bunch of other places in softfloat.c which switch on the float rounding mode. If this rounding mode is only supported for a particular subset of operations we should at least document that in the comment. thanks -- PMM
On 5/18/21 6:20 AM, Peter Maydell wrote: > This code change looks OK as far as it goes, but there are a bunch > of other places in softfloat.c which switch on the float rounding mode. > If this rounding mode is only supported for a particular subset of > operations we should at least document that in the comment. Once the softfloat reorg is complete, there will be only one place to add this. I didn't want to go overboard on that here, or necessarily depend on more that just SVE2 for now. r~
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8a3f20fae9..3b757c3d6a 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -134,8 +134,10 @@ typedef enum __attribute__((__packed__)) { float_round_up = 2, float_round_to_zero = 3, float_round_ties_away = 4, - /* Not an IEEE rounding mode: round to the closest odd mantissa value */ + /* Not an IEEE rounding mode: round to closest odd, overflow to max */ float_round_to_odd = 5, + /* Not an IEEE rounding mode: round to closest odd, overflow to inf */ + float_round_to_odd_inf = 6, } FloatRoundMode; /* diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 67cfa0fd82..76097679b0 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -694,13 +694,12 @@ static FloatParts round_canonical(FloatParts p, float_status *s, switch (p.cls) { case float_class_normal: + overflow_norm = false; switch (s->float_rounding_mode) { case float_round_nearest_even: - overflow_norm = false; inc = ((frac & roundeven_mask) != frac_lsbm1 ? frac_lsbm1 : 0); break; case float_round_ties_away: - overflow_norm = false; inc = frac_lsbm1; break; case float_round_to_zero: @@ -717,6 +716,8 @@ static FloatParts round_canonical(FloatParts p, float_status *s, break; case float_round_to_odd: overflow_norm = true; + /* fall through */ + case float_round_to_odd_inf: inc = frac & frac_lsb ? 0 : round_mask; break; default: @@ -771,6 +772,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s, ? frac_lsbm1 : 0); break; case float_round_to_odd: + case float_round_to_odd_inf: inc = frac & frac_lsb ? 0 : round_mask; break; default: @@ -6860,6 +6862,8 @@ float128 float128_round_to_int(float128 a, float_status *status) case float_round_to_zero: break; + default: + g_assert_not_reached(); } return packFloat128( aSign, 0, 0, 0 ); }
For Arm BFDOT and BFMMLA, we need a version of round-to-odd that overflows to infinity, instead of the max normal number. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- include/fpu/softfloat-types.h | 4 +++- fpu/softfloat.c | 8 ++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) -- 2.25.1