diff mbox series

[RESEND] mmc: sdhci-pci-gli: Improve GL9763E L1 entry delay to increase battery life

Message ID 20210407093816.8863-1-benchuanggli@gmail.com
State Superseded
Headers show
Series [RESEND] mmc: sdhci-pci-gli: Improve GL9763E L1 entry delay to increase battery life | expand

Commit Message

Ben Chuang April 7, 2021, 9:38 a.m. UTC
From: Ben Chuang <ben.chuang@genesyslogic.com.tw>

For GL9763E, although there is the best performance at the maximum delay.
Change the value to 20us in order to have better power consumption.
This change may reduce the maximum performance by 10%.

Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
---
 drivers/mmc/host/sdhci-pci-gli.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Ulf Hansson April 12, 2021, 7:52 a.m. UTC | #1
On Wed, 7 Apr 2021 at 11:35, Ben Chuang <benchuanggli@gmail.com> wrote:
>

> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>

>

> For GL9763E, although there is the best performance at the maximum delay.

> Change the value to 20us in order to have better power consumption.

> This change may reduce the maximum performance by 10%.

>

> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>


Applied for next, thanks!

Kind regards
Uffe


> ---

>  drivers/mmc/host/sdhci-pci-gli.c | 6 +++---

>  1 file changed, 3 insertions(+), 3 deletions(-)

>

> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c

> index 4a0f69b97a78..3b0a049d4124 100644

> --- a/drivers/mmc/host/sdhci-pci-gli.c

> +++ b/drivers/mmc/host/sdhci-pci-gli.c

> @@ -90,7 +90,7 @@

>

>  #define PCIE_GLI_9763E_CFG2      0x8A4

>  #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)

> -#define   GLI_9763E_CFG2_L1DLY_MAX 0x3FF

> +#define   GLI_9763E_CFG2_L1DLY_MID 0x50

>

>  #define PCIE_GLI_9763E_MMC_CTRL  0x960

>  #define   GLI_9763E_HS400_SLOW     BIT(3)

> @@ -802,8 +802,8 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)

>

>         pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);

>         value &= ~GLI_9763E_CFG2_L1DLY;

> -       /* set ASPM L1 entry delay to 260us */

> -       value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX);

> +       /* set ASPM L1 entry delay to 20us */

> +       value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);

>         pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);

>

>         pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);

> --

> 2.30.0

>
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 4a0f69b97a78..3b0a049d4124 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -90,7 +90,7 @@ 
 
 #define PCIE_GLI_9763E_CFG2      0x8A4
 #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
-#define   GLI_9763E_CFG2_L1DLY_MAX 0x3FF
+#define   GLI_9763E_CFG2_L1DLY_MID 0x50
 
 #define PCIE_GLI_9763E_MMC_CTRL  0x960
 #define   GLI_9763E_HS400_SLOW     BIT(3)
@@ -802,8 +802,8 @@  static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
 
 	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
 	value &= ~GLI_9763E_CFG2_L1DLY;
-	/* set ASPM L1 entry delay to 260us */
-	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX);
+	/* set ASPM L1 entry delay to 20us */
+	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
 	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
 
 	pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);