| Message ID | 20210406141819.1025864-2-dqfext@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MT7530 interrupt support | expand |
On Tue, Apr 06, 2021 at 10:18:16PM +0800, DENG Qingfang wrote: > Add support for MediaTek PHYs found in MT7530 and MT7531 switches. Do you know if this PHY is available standalone? > +static int mt7531_phy_config_init(struct phy_device *phydev) > +{ > + mtk_phy_config_init(phydev); > + > + /* PHY link down power saving enable */ > + phy_set_bits(phydev, 0x17, BIT(4)); > + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); > + > + /* Set TX Pair delay selection */ > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); This gets me worried about RGMII delays. We have had bad backwards compatibility problems with PHY drivers which get RGMII delays wrong. Since this is an internal PHY, i suggest you add a test to the beginning of mt7531_phy_config_init(): if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) return -EINVAL; We can then solve RGMII problems when somebody actually needs RGMII. Andrew
On Tue, Apr 6, 2021 at 11:21 PM Andrew Lunn <andrew@lunn.ch> wrote: > > On Tue, Apr 06, 2021 at 10:18:16PM +0800, DENG Qingfang wrote: > > Add support for MediaTek PHYs found in MT7530 and MT7531 switches. > > Do you know if this PHY is available standalone? Not that I know of. > > > +static int mt7531_phy_config_init(struct phy_device *phydev) > > +{ > > + mtk_phy_config_init(phydev); > > + > > + /* PHY link down power saving enable */ > > + phy_set_bits(phydev, 0x17, BIT(4)); > > + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); > > + > > + /* Set TX Pair delay selection */ > > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); > > + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); > > This gets me worried about RGMII delays. We have had bad backwards > compatibility problems with PHY drivers which get RGMII delays wrong. > > Since this is an internal PHY, i suggest you add a test to the > beginning of mt7531_phy_config_init(): > > if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) > return -EINVAL; Okay. Will add it to v2. > > We can then solve RGMII problems when somebody actually needs RGMII. > > Andrew
On Tue, Apr 6, 2021 at 11:47 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote: > > Hi, Qingfang: > > DENG Qingfang <dqfext@gmail.com> 於 2021年4月6日 週二 下午10:19寫道： > > --- a/drivers/net/phy/Kconfig > > +++ b/drivers/net/phy/Kconfig > > @@ -207,6 +207,11 @@ config MARVELL_88X2222_PHY > > Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet > > Transceiver. > > > > +config MEDIATEK_PHY > > There are many Mediatek phy drivers in [1], so use a specific name. So "MEDIATEK_MT7530_PHY" should be okay? > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/phy/mediatek?h=v5.12-rc6 > > Regards, > Chun-Kuang.
On Tue, Apr 06, 2021 at 11:57:14PM +0800, DENG Qingfang wrote: > On Tue, Apr 6, 2021 at 11:47 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote: > > > > Hi, Qingfang: > > > > DENG Qingfang <dqfext@gmail.com> 於 2021年4月6日 週二 下午10:19寫道： > > > --- a/drivers/net/phy/Kconfig > > > +++ b/drivers/net/phy/Kconfig > > > @@ -207,6 +207,11 @@ config MARVELL_88X2222_PHY > > > Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet > > > Transceiver. > > > > > > +config MEDIATEK_PHY > > > > There are many Mediatek phy drivers in [1], so use a specific name. > > So "MEDIATEK_MT7530_PHY" should be okay? No. MEDIATEK_PHY is consistent with other PHY drivers. Please leave it as it is. And with time, we expect other devices will be supported by this driver, so having MT7530 in the name would be confusing. Andrew
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index a615b3660b05..edd858cec9ec 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -207,6 +207,11 @@ config MARVELL_88X2222_PHY Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet Transceiver. +config MEDIATEK_PHY + tristate "MediaTek PHYs" + help + Supports the MediaTek switch integrated PHYs. + config MICREL_PHY tristate "Micrel PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index de683e3abe63..9ed7dbab7770 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o +obj-$(CONFIG_MEDIATEK_PHY) += mediatek.o obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o obj-$(CONFIG_MICREL_PHY) += micrel.o diff --git a/drivers/net/phy/mediatek.c b/drivers/net/phy/mediatek.c new file mode 100644 index 000000000000..18fefd79a9bd --- /dev/null +++ b/drivers/net/phy/mediatek.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <linux/module.h> +#include <linux/phy.h> +#include <linux/version.h> + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED 0x0001 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +static int mtk_phy_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} + +static int mtk_phy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} + +static void mtk_phy_config_init(struct phy_device *phydev) +{ + /* Disable EEE */ + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); + + /* Enable HW auto downshift */ + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); + + /* Increase SlvDPSready time */ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __phy_write(phydev, 0x10, 0xafae); + __phy_write(phydev, 0x12, 0x2f); + __phy_write(phydev, 0x10, 0x8fae); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* Adjust 100_mse_threshold */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); + + /* Disable mcc */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); +} + +static int mt7530_phy_config_init(struct phy_device *phydev) +{ + mtk_phy_config_init(phydev); + + /* Increase post_update_timer */ + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); + + return 0; +} + +static int mt7531_phy_config_init(struct phy_device *phydev) +{ + mtk_phy_config_init(phydev); + + /* PHY link down power saving enable */ + phy_set_bits(phydev, 0x17, BIT(4)); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); + + /* Set TX Pair delay selection */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); + + return 0; +} + +static struct phy_driver mtk_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(0x03a29412), + .name = "MediaTek MT7530 PHY", + .config_init = mt7530_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, + }, + { + PHY_ID_MATCH_EXACT(0x03a29441), + .name = "MediaTek MT7531 PHY", + .config_init = mt7531_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, + }, +}; + +module_phy_driver(mtk_phy_driver); + +static struct mdio_device_id __maybe_unused mtk_phy_tbl[] = { + { PHY_ID_MATCH_VENDOR(0x03a29400) }, + { } +}; + +MODULE_DESCRIPTION("MediaTek switch integrated PHY driver"); +MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>"); +MODULE_LICENSE("GPL"); + +MODULE_DEVICE_TABLE(mdio, mtk_phy_tbl);
Add support for MediaTek PHYs found in MT7530 and MT7531 switches. The initialization procedure is from the vendor driver, but due to lack of documentation, the function of some register values remains unknown. Signed-off-by: DENG Qingfang <dqfext@gmail.com> --- drivers/net/phy/Kconfig | 5 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mediatek.c | 109 +++++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) create mode 100644 drivers/net/phy/mediatek.c