@@ -671,6 +671,12 @@ static int stm32_usart_startup(struct uart_port *port)
if (ret)
return ret;
+ if (stm32_port->swap) {
+ val = readl_relaxed(port->membase + ofs->cr2);
+ val |= USART_CR2_SWAP;
+ writel_relaxed(val, port->membase + ofs->cr2);
+ }
+
/* RX FIFO Flush */
if (ofs->rqr != UNDEF_REG)
writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
@@ -789,7 +795,7 @@ static void stm32_usart_set_termios(struct uart_port *port,
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN;
- cr2 = 0;
+ cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
/* Tx and RX FIFO configuration */
cr3 = readl_relaxed(port->membase + ofs->cr3);
@@ -1047,6 +1053,9 @@ static int stm32_usart_init_port(struct stm32_port *stm32port,
stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
of_property_read_bool(pdev->dev.of_node, "wakeup-source");
+ stm32port->swap = stm32port->info->cfg.has_swap &&
+ of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
+
stm32port->fifoen = stm32port->info->cfg.has_fifo;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -25,6 +25,7 @@ struct stm32_usart_offsets {
struct stm32_usart_config {
u8 uart_enable_bit; /* USART_CR1_UE */
bool has_7bits_data;
+ bool has_swap;
bool has_wakeup;
bool has_fifo;
int fifosize;
@@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+ .has_swap = true,
.fifosize = 1,
}
};
@@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = {
.cfg = {
.uart_enable_bit = 0,
.has_7bits_data = true,
+ .has_swap = true,
.has_wakeup = true,
.has_fifo = true,
.fifosize = 16,
@@ -268,6 +271,7 @@ struct stm32_port {
int last_res;
bool tx_dma_busy; /* dma tx busy */
bool hw_flow_control;
+ bool swap; /* swap RX & TX pins */
bool fifoen;
bool wakeup_src;
int rdr_mask; /* receive data register mask */