Message ID | 1616837358-15112-1-git-send-email-liulongfang@huawei.com |
---|---|
State | Accepted |
Commit | da6503f52bf85a7da29fbd7126320658f906dd9a |
Headers | show |
Series | crypto: hisilicon/sec - Fix a module parameter error | expand |
On 2021/3/27 17:29, Longfang Liu Wrote: > ctx_q_num is a module parameter set by the user to specify the > number of qp queues required to create a ctx. > > When the number of qp queues allocated by PF or VF is less than > the ctx_q_num, an error will be reported when ctx is initialized > in kernel mode, which leads to the problem that the registered > algorithms cannot be used. > > Therefore, when PF or VF is initialized, if the number of qp queues > is not enough to create a ctx, the kernel mode cannot be used, > and there is no need to register the kernel mode algorithms. > > Signed-off-by: Longfang Liu <liulongfang@huawei.com> > --- > drivers/crypto/hisilicon/sec2/sec_main.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c > index b1818f7..c7b71b6 100644 > --- a/drivers/crypto/hisilicon/sec2/sec_main.c > +++ b/drivers/crypto/hisilicon/sec2/sec_main.c > @@ -867,10 +867,15 @@ static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) > if (ret) > pci_warn(pdev, "Failed to init debugfs!\n"); > > - ret = hisi_qm_alg_register(qm, &sec_devices); > - if (ret < 0) { > - pr_err("Failed to register driver to crypto.\n"); > - goto err_qm_stop; > + if (qm->qp_num >= ctx_q_num) { > + ret = hisi_qm_alg_register(qm, &sec_devices); > + if (ret < 0) { > + pr_err("Failed to register driver to crypto.\n"); > + goto err_qm_stop; > + } > + } else { > + pci_warn(qm->pdev, > + "Failed to use kernel mode, qp not enough!\n"); > } > > if (qm->uacce) { > Sorry, please don't reply to this patch, I will resend it again. Thanks, Longfang
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c b/drivers/crypto/hisilicon/sec2/sec_main.c index b1818f7..c7b71b6 100644 --- a/drivers/crypto/hisilicon/sec2/sec_main.c +++ b/drivers/crypto/hisilicon/sec2/sec_main.c @@ -867,10 +867,15 @@ static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (ret) pci_warn(pdev, "Failed to init debugfs!\n"); - ret = hisi_qm_alg_register(qm, &sec_devices); - if (ret < 0) { - pr_err("Failed to register driver to crypto.\n"); - goto err_qm_stop; + if (qm->qp_num >= ctx_q_num) { + ret = hisi_qm_alg_register(qm, &sec_devices); + if (ret < 0) { + pr_err("Failed to register driver to crypto.\n"); + goto err_qm_stop; + } + } else { + pci_warn(qm->pdev, + "Failed to use kernel mode, qp not enough!\n"); } if (qm->uacce) {
ctx_q_num is a module parameter set by the user to specify the number of qp queues required to create a ctx. When the number of qp queues allocated by PF or VF is less than the ctx_q_num, an error will be reported when ctx is initialized in kernel mode, which leads to the problem that the registered algorithms cannot be used. Therefore, when PF or VF is initialized, if the number of qp queues is not enough to create a ctx, the kernel mode cannot be used, and there is no need to register the kernel mode algorithms. Signed-off-by: Longfang Liu <liulongfang@huawei.com> --- drivers/crypto/hisilicon/sec2/sec_main.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)