@@ -64,6 +64,7 @@
#define OMAP_HSMMC_ISE 0x0138
#define OMAP_HSMMC_AC12 0x013C
#define OMAP_HSMMC_CAPA 0x0140
+#define OMAP_HSMMC_CAPA2 0x0144
#define VS18 (1 << 26)
#define VS30 (1 << 25)
@@ -139,6 +140,10 @@
#define ACTO (1 << 1)
#define ACNE (1 << 0)
+#define SDR50 (1 << 0)
+#define SDR104 (1 << 1)
+#define DDR50 (1 << 2)
+
#define MMC_AUTOSUSPEND_DELAY 100
#define MMC_TIMEOUT_MS 20 /* 20 mSec */
#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
@@ -2028,6 +2033,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
unsigned tx_req, rx_req;
const struct omap_mmc_of_data *data;
void __iomem *base;
+ u32 reg;
match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
if (match) {
@@ -2153,6 +2159,19 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
mmc->pm_caps = mmc_slot(host).pm_caps;
+ reg = OMAP_HSMMC_READ(host->base, OMAP_HSMMC_CAPA2);
+
+ if (reg & SDR50)
+ mmc->caps |= MMC_CAP_UHS_DDR50;
+
+ if (reg & SDR104) {
+ mmc->caps |= MMC_CAP_UHS_SDR104;
+ mmc->caps2 |= MMC_CAP2_HS200;
+ }
+
+ if (reg & DDR50)
+ mmc->caps |= MMC_CAP_UHS_DDR50;
+
omap_hsmmc_conf_bus_power(host);
if (!pdev->dev.of_node) {