| Message ID | 1414704538-17103-20-git-send-email-greg.bellows@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30 October 2014 21:28, Greg Bellows <greg.bellows@linaro.org> wrote: > From: Fabian Aggeler <aggelerf@ethz.ch> > > When EL3 is running in AArch32 (or ARMv7 with Security Extensions) > DACR has a secure and a non-secure instance. > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > --- > hw/arm/pxa2xx.c | 2 +- > target-arm/cpu.h | 13 +++++++++++-- > target-arm/helper.c | 19 +++++++++++-------- > 3 files changed, 23 insertions(+), 11 deletions(-) > > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c > index 641b148..ac13d0b 100644 > --- a/hw/arm/pxa2xx.c > +++ b/hw/arm/pxa2xx.c > @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, > s->cpu->env.cp15.sctlr_ns = 0; > s->cpu->env.cp15.c1_coproc = 0; > s->cpu->env.cp15.ttbr0_el[1] = 0; > - s->cpu->env.cp15.c3 = 0; > + s->cpu->env.cp15.dacr_ns = 0; > s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ > s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 6e9f1c3..6d39af1 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -236,8 +236,17 @@ typedef struct CPUARMState { > }; > uint32_t c2_data; /* MPU data cachable bits. */ > uint32_t c2_insn; /* MPU instruction cachable bits. */ > - uint32_t c3; /* MMU domain access control register > - MPU write buffer control. */ > + union { /* MMU domain access control register > + * MPU write buffer control. > + */ > + struct { > + uint32_t dacr_ns; > + uint32_t dacr_s; > + }; > + struct { > + uint32_t dacr32_el2; > + }; If we're going to define a dacr32_el2 field here we should actually implement the reginfo for it (it just has to be a simple reads-as-written PL2_RW register). It's also going to have to be uint64_t, which means the dacr_ns/dacr_s fields also should be 64 bit. Someday we should split out the MPU use of this encoding properly into its own field because it isn't anything to do with the DACR. I guess not today, though. -- PMM
Added DACR32_EL2 definition and converted dacr fields to uint64_t in v9. On 31 October 2014 10:38, Peter Maydell <peter.maydell@linaro.org> wrote: > On 30 October 2014 21:28, Greg Bellows <greg.bellows@linaro.org> wrote: > > From: Fabian Aggeler <aggelerf@ethz.ch> > > > > When EL3 is running in AArch32 (or ARMv7 with Security Extensions) > > DACR has a secure and a non-secure instance. > > > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > > --- > > hw/arm/pxa2xx.c | 2 +- > > target-arm/cpu.h | 13 +++++++++++-- > > target-arm/helper.c | 19 +++++++++++-------- > > 3 files changed, 23 insertions(+), 11 deletions(-) > > > > diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c > > index 641b148..ac13d0b 100644 > > --- a/hw/arm/pxa2xx.c > > +++ b/hw/arm/pxa2xx.c > > @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, > const ARMCPRegInfo *ri, > > s->cpu->env.cp15.sctlr_ns = 0; > > s->cpu->env.cp15.c1_coproc = 0; > > s->cpu->env.cp15.ttbr0_el[1] = 0; > > - s->cpu->env.cp15.c3 = 0; > > + s->cpu->env.cp15.dacr_ns = 0; > > s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ > > s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index 6e9f1c3..6d39af1 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -236,8 +236,17 @@ typedef struct CPUARMState { > > }; > > uint32_t c2_data; /* MPU data cachable bits. */ > > uint32_t c2_insn; /* MPU instruction cachable bits. */ > > - uint32_t c3; /* MMU domain access control register > > - MPU write buffer control. */ > > + union { /* MMU domain access control register > > + * MPU write buffer control. > > + */ > > + struct { > > + uint32_t dacr_ns; > > + uint32_t dacr_s; > > + }; > > + struct { > > + uint32_t dacr32_el2; > > + }; > > If we're going to define a dacr32_el2 field here we should > actually implement the reginfo for it (it just has to be a > simple reads-as-written PL2_RW register). It's also going to > have to be uint64_t, which means the dacr_ns/dacr_s fields > also should be 64 bit. > > Someday we should split out the MPU use of this encoding > properly into its own field because it isn't anything to > do with the DACR. I guess not today, though. > > -- PMM >
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 641b148..ac13d0b 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -276,7 +276,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.cp15.sctlr_ns = 0; s->cpu->env.cp15.c1_coproc = 0; s->cpu->env.cp15.ttbr0_el[1] = 0; - s->cpu->env.cp15.c3 = 0; + s->cpu->env.cp15.dacr_ns = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6e9f1c3..6d39af1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -236,8 +236,17 @@ typedef struct CPUARMState { }; uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ - uint32_t c3; /* MMU domain access control register - MPU write buffer control. */ + union { /* MMU domain access control register + * MPU write buffer control. + */ + struct { + uint32_t dacr_ns; + uint32_t dacr_s; + }; + struct { + uint32_t dacr32_el2; + }; + }; uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 27eaf9c..eaae534 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -437,8 +437,10 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = { /* MMU Domain access control / MPU write buffer control */ { .name = "DACR", .cp = 15, .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), - .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, + .access = PL1_RW, .resetvalue = 0, + .writefn = dacr_write, .raw_writefn = raw_write, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dacr_s), + offsetof(CPUARMState, cp15.dacr_ns) } }, /* ??? This covers not just the impdef TLB lockdown registers but also * some v7VMSA registers relating to TEX remap, so it is overly broad. */ @@ -2256,10 +2258,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, .type = ARM_CP_NOP, .access = PL1_W }, /* MMU Domain access control / MPU write buffer control */ - { .name = "DACR", .cp = 15, - .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), - .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, }, + { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .writefn = dacr_write, .raw_writefn = raw_write, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dacr_s), + offsetof(CPUARMState, cp15.dacr_ns) } }, { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1, @@ -4494,7 +4497,7 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, desc = ldl_phys(cs->as, table); type = (desc & 3); domain = (desc >> 5) & 0x0f; - domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; + domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3; if (type == 0) { /* Section translation fault. */ code = 5; @@ -4606,7 +4609,7 @@ static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type, /* Page or Section. */ domain = (desc >> 5) & 0x0f; } - domain_prot = (env->cp15.c3 >> (domain * 2)) & 3; + domain_prot = (A32_BANKED_CURRENT_REG_GET(env, dacr) >> (domain * 2)) & 3; if (domain_prot == 0 || domain_prot == 2) { if (type != 1) { code = 9; /* Section domain fault. */