| Message ID | 1615476112-113101-4-git-send-email-zhouyanjie@wanyeetech.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix bugs and add support for new Ingenic SoCs. | expand |
Le jeu. 11 mars 2021 à 23:21, 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> a écrit : > Adjust the sequence of X1830's SSI related codes to make it consistent > with other Ingenic SoCs. > > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Cheers, -Paul > --- > > Notes: > v2: > New patch. > > drivers/pinctrl/pinctrl-ingenic.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-ingenic.c > b/drivers/pinctrl/pinctrl-ingenic.c > index 0a88aab..607ba0b 100644 > --- a/drivers/pinctrl/pinctrl-ingenic.c > +++ b/drivers/pinctrl/pinctrl-ingenic.c > @@ -1473,16 +1473,16 @@ static int x1830_ssi0_gpc_pins[] = { 0x4d, }; > static int x1830_ssi0_ce0_pins[] = { 0x50, }; > static int x1830_ssi0_ce1_pins[] = { 0x4e, }; > static int x1830_ssi1_dt_c_pins[] = { 0x53, }; > -static int x1830_ssi1_dr_c_pins[] = { 0x54, }; > -static int x1830_ssi1_clk_c_pins[] = { 0x57, }; > -static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; > -static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; > -static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; > static int x1830_ssi1_dt_d_pins[] = { 0x62, }; > +static int x1830_ssi1_dr_c_pins[] = { 0x54, }; > static int x1830_ssi1_dr_d_pins[] = { 0x63, }; > +static int x1830_ssi1_clk_c_pins[] = { 0x57, }; > static int x1830_ssi1_clk_d_pins[] = { 0x66, }; > +static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; > static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; > +static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; > static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; > +static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; > static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; > static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; > static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; > -- > 2.7.4 >
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 0a88aab..607ba0b 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1473,16 +1473,16 @@ static int x1830_ssi0_gpc_pins[] = { 0x4d, }; static int x1830_ssi0_ce0_pins[] = { 0x50, }; static int x1830_ssi0_ce1_pins[] = { 0x4e, }; static int x1830_ssi1_dt_c_pins[] = { 0x53, }; -static int x1830_ssi1_dr_c_pins[] = { 0x54, }; -static int x1830_ssi1_clk_c_pins[] = { 0x57, }; -static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; -static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; -static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; static int x1830_ssi1_dt_d_pins[] = { 0x62, }; +static int x1830_ssi1_dr_c_pins[] = { 0x54, }; static int x1830_ssi1_dr_d_pins[] = { 0x63, }; +static int x1830_ssi1_clk_c_pins[] = { 0x57, }; static int x1830_ssi1_clk_d_pins[] = { 0x66, }; +static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; +static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; +static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
Adjust the sequence of X1830's SSI related codes to make it consistent with other Ingenic SoCs. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> --- Notes: v2: New patch. drivers/pinctrl/pinctrl-ingenic.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)