| Message ID | 20210310163024.393578-2-caleb@connolly.tech |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] arm64: dts: qcom: sm8150: add other QUP nodes | expand |
Hello Caleb, On Wed, 10 Mar 2021 at 22:02, Caleb Connolly <caleb@connolly.tech> wrote: > > Add the first and third qupv3 nodes used to hook > up peripherals on some devices. > > Signed-off-by: Caleb Connolly <caleb@connolly.tech> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index e5bb17bc2f46..03e05d98daf2 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -577,6 +577,18 @@ gcc: clock-controller@100000 { > <&sleep_clk>; > }; > > + qupv3_id_0: geniqup@8c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x008c0000 0x0 0x6000>; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + }; > + > qupv3_id_1: geniqup@ac0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x0 0x00ac0000 0x0 0x6000>; > @@ -598,6 +610,19 @@ uart2: serial@a90000 { > }; > }; > > + qupv3_id_2: geniqup@cc0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x00cc0000 0x0 0x6000>; > + > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + }; > + > config_noc: interconnect@1500000 { > compatible = "qcom,sm8150-config-noc"; > reg = <0 0x01500000 0 0x7400>; LGTM, so: Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e5bb17bc2f46..03e05d98daf2 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -577,6 +577,18 @@ gcc: clock-controller@100000 { <&sleep_clk>; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -598,6 +610,19 @@ uart2: serial@a90000 { }; }; + qupv3_id_2: geniqup@cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00cc0000 0x0 0x6000>; + + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8150-config-noc"; reg = <0 0x01500000 0 0x7400>;
Add the first and third qupv3 nodes used to hook up peripherals on some devices. Signed-off-by: Caleb Connolly <caleb@connolly.tech> --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)