| Message ID | 20210214174453.104616-1-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/2] dt-bindings: display: bridge: Add bindings for SN65DSI83/84/85 | expand |
Hi, On 15/02/2021 12:25, Jagan Teki wrote: > On Mon, Feb 15, 2021 at 2:32 PM Neil Armstrong <narmstrong@baylibre.com> wrote: >> >> Hi, >> >> On 14/02/2021 18:44, Jagan Teki wrote: >>> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge >>> controller IC's from Texas Instruments. >>> >>> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge >>> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge >>> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge >>> >>> Right now the bridge driver is supporting Channel A with single >>> link, so dt-bindings documented according to it. >> >> Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ? > > Patch documented only Single link LVDS as it only supported by driver. > Single link LVDS with Channel A configuration is common across all 3 > variant chips. I have SN65DSI84 with Single link LVDS which is routed > in Channel A. Idea is to go with Single link and add double link later > and document the same. DT Bindings is unrelated to the software support, simply add the second LVDS channel endpoint for SN65DSI84/85 and the second dsi endpoint for SN65DSI85. Neil > > Jagan. >
On Sun, 14 Feb 2021 23:14:52 +0530, Jagan Teki wrote: > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge > controller IC's from Texas Instruments. > > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge > > Right now the bridge driver is supporting Channel A with single > link, so dt-bindings documented according to it. > > Cc: Marek Vasut <marex@denx.de> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > Changes for v3: > - fixed Rob comments > - updated commit message and file name to support all chip variants > Changes for v2: > - none > > .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++ > 1 file changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
On 2/14/21 6:44 PM, Jagan Teki wrote: > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge > controller IC's from Texas Instruments. > > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge [...] > +description: | > + SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller > + IC's from Texas Instruments. > + > + SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > + SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > + SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge [...] > +properties: > + compatible: > + enum: > + - ti,sn65dsi83 > + - ti,sn65dsi84 DSI85 seems missing ? > + reg: > + const: 0x2c I have the DSI83 device at 0x2d, so this cannot be const 0x2c ? > + enable-gpios: > + maxItems: 1 > + description: GPIO specifier for bridge enable pin (active high). The bridge can work without this GPIO, so its optional. [...] Also, Doug reported that vcc and vcore regulators should likely be listed, see feedback on: [PATCH 1/2] dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 bindings
On 2/14/21 6:44 PM, Jagan Teki wrote: [...] > +static const struct regmap_config sn65dsi_regmap_config = { > + .reg_bits = 8, > + .val_bits = 8, > + .max_register = SN65DSI_CHA_ERR, > + .name = "sn65dsi", > + .cache_type = REGCACHE_RBTREE, > +}; You might want to look at the driver I posted one more time, it defines the regmap precisely and limits each register access, see: [PATCH 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 driver that way it can be dumped via debugfs and the regmap does not cache registers which do not exist, like it does here. [...] > +static int sn65dsi_get_clk_range(int min, int max, unsigned long clock, > + unsigned long start, unsigned long diff) > +{ > + unsigned long next; > + int i; > + > + for (i = min; i <= max; i++) { > + next = start + diff; > + if (start <= clock && clock < next) > + return i; > + > + start += diff; > + } > + > + return -EINVAL; > +} The clock rates can be calculated in linear time, see the driver above, it is implemented there. > +static void sn65dsi_enable(struct drm_bridge *bridge) > +{ > + struct sn65dsi *sn = bridge_to_sn65dsi(bridge); > + struct drm_display_mode *mode = bridge_to_mode(bridge); > + int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format); > + unsigned int lanes = sn->dsi->lanes; > + unsigned int pixel_clk = mode->clock * 1000; > + unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2); > + unsigned int val; > + > + /* reset SOFT_RESET bit */ > + regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0); > + > + msleep(10); Why is there msleep(10) all over the place ? I don't see such a requirement listed anywhere in the DSI83 datasheet. > + /* reset PLL_EN bit */ > + regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0); > + > + msleep(10); Here too. [...] You also want to check the feedback on the driver I posted, it deals with polling for the PLL to be ready, which seems to be missing here. That should remove most of the msleep() calls.
Hi Jagan, On 2021-02-14 18:44, Jagan Teki wrote: [...] > +static void sn65dsi_enable(struct drm_bridge *bridge) > +{ > + struct sn65dsi *sn = bridge_to_sn65dsi(bridge); > + struct drm_display_mode *mode = bridge_to_mode(bridge); > + int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format); > + unsigned int lanes = sn->dsi->lanes; > + unsigned int pixel_clk = mode->clock * 1000; > + unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2); > + unsigned int val; > + > + /* reset SOFT_RESET bit */ > + regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0); > + > + msleep(10); > + > + /* reset PLL_EN bit */ > + regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0); > + > + msleep(10); > + > + /* setup lvds clock */ > + val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000); > + if (val < 0) { val is unsigned int, so it can never be negative so this condition is always false. Same error further down in that function as well. regards, Claudius
Hi Jagan, On 2021-02-14 18:44, Jagan Teki wrote: > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge > controller IC's from Texas Instruments. > > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge > > Right now the bridge driver is supporting Channel A with single > link, so dt-bindings documented according to it. Do you know when we can expect a v4 for this? I am currently working on top of your patch set to setup a dual-link LVDS bridge of SN65DSI84. thanks and kind regards, Claudius
Hi again, On Wed, Mar 24, 2021 at 02:56:37PM +0100, Claudius Heine wrote: > Hi Jagan, > > On 2021-02-14 18:44, Jagan Teki wrote: > > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge > > controller IC's from Texas Instruments. > > > > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge > > > > Right now the bridge driver is supporting Channel A with single > > link, so dt-bindings documented according to it. > > Do you know when we can expect a v4 for this? > > I am currently working on top of your patch set to setup a dual-link LVDS > bridge of SN65DSI84. Ping
On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine <ch@denx.de> wrote: > > Hi Jagan, > > On 2021-02-14 18:44, Jagan Teki wrote: > > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge > > controller IC's from Texas Instruments. > > > > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge > > > > Right now the bridge driver is supporting Channel A with single > > link, so dt-bindings documented according to it. > > Do you know when we can expect a v4 for this? > > I am currently working on top of your patch set to setup a dual-link > LVDS bridge of SN65DSI84. Yes, I'm planning to send v4 this week. will keep you in CC. thanks! Jagan.
On 4/8/21 4:45 PM, Jagan Teki wrote: > On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine <ch@denx.de> wrote: >> >> Hi Jagan, >> >> On 2021-02-14 18:44, Jagan Teki wrote: >>> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge >>> controller IC's from Texas Instruments. >>> >>> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge >>> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge >>> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge >>> >>> Right now the bridge driver is supporting Channel A with single >>> link, so dt-bindings documented according to it. >> >> Do you know when we can expect a v4 for this? >> >> I am currently working on top of your patch set to setup a dual-link >> LVDS bridge of SN65DSI84. > > Yes, I'm planning to send v4 this week. will keep you in CC. thanks! I haven't seen any activity here for over two weeks, so I decided to send V2 of the driver I wrote, now tested on both DSI83 and DSI84.
On Thu, Apr 22, 2021 at 4:04 AM Marek Vasut <marex@denx.de> wrote: > > On 4/8/21 4:45 PM, Jagan Teki wrote: > > On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine <ch@denx.de> wrote: > >> > >> Hi Jagan, > >> > >> On 2021-02-14 18:44, Jagan Teki wrote: > >>> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge > >>> controller IC's from Texas Instruments. > >>> > >>> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge > >>> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge > >>> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge > >>> > >>> Right now the bridge driver is supporting Channel A with single > >>> link, so dt-bindings documented according to it. > >> > >> Do you know when we can expect a v4 for this? > >> > >> I am currently working on top of your patch set to setup a dual-link > >> LVDS bridge of SN65DSI84. > > > > Yes, I'm planning to send v4 this week. will keep you in CC. thanks! > > I haven't seen any activity here for over two weeks, so I decided to > send V2 of the driver I wrote, now tested on both DSI83 and DSI84. It delayed me since I have considered several comments from the Mailing list to wrote Dual Link-LVDS configuration support. I have a plan to send v4 in the coming weekend with these changes, I thought it would be the possible driver to support 1 and 2 links LVDS. Jagan.
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml new file mode 100644 index 000000000000..7f9f8cd6e786 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings + +maintainers: + - Jagan Teki <jagan@amarulasolutions.com> + +description: | + SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller + IC's from Texas Instruments. + + SN65DSI83 - Single Channel DSI to Single-link LVDS bridge + SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge + SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge + + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and + converts the formatted video data stream to a FlatLink compatible + LVDS output operating at pixel clocks operating from 25 MHx to + 154 MHz. + +properties: + compatible: + enum: + - ti,sn65dsi83 + - ti,sn65dsi84 + + reg: + const: 0x2c + + enable-gpios: + maxItems: 1 + description: GPIO specifier for bridge enable pin (active high). + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: | + DSI Input. The remote endpoint phandle should be a + reference to a valid mipi_dsi_host device node. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + Video port for LVDS output (panel or connector). + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + data-lanes = <0 1>; + }; + }; + }; + }; + + i2c6 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + };
SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller IC's from Texas Instruments. SN65DSI83 - Single Channel DSI to Single-link LVDS bridge SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge Right now the bridge driver is supporting Channel A with single link, so dt-bindings documented according to it. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v3: - fixed Rob comments - updated commit message and file name to support all chip variants Changes for v2: - none .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml