diff mbox series

drivers: media: pci: cx18: Couple of spell fixes in the file cx18-av-core.c

Message ID 20210213150805.1606638-1-unixbhaskar@gmail.com
State Accepted
Commit 611ce3395e34cc20cb07c507314d77c1bb4a06ca
Headers show
Series drivers: media: pci: cx18: Couple of spell fixes in the file cx18-av-core.c | expand

Commit Message

Bhaskar Chowdhury Feb. 13, 2021, 3:08 p.m. UTC 
s/minimze/minimize/
s/initallize/initialize/

Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
---
 drivers/media/pci/cx18/cx18-av-core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--
2.30.1
diff mbox series

Patch

diff --git a/drivers/media/pci/cx18/cx18-av-core.c b/drivers/media/pci/cx18/cx18-av-core.c
index b33eb08631b1..11cfe35fd730 100644
--- a/drivers/media/pci/cx18/cx18-av-core.c
+++ b/drivers/media/pci/cx18/cx18-av-core.c
@@ -89,7 +89,7 @@  static void cx18_av_init(struct cx18 *cx)
 	/*
 	 * The crystal freq used in calculations in this driver will be
 	 * 28.636360 MHz.
-	 * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
+	 * Aim to run the PLLs' VCOs near 400 MHz to minimize errors.
 	 */

 	/*
@@ -122,7 +122,7 @@  static void cx18_av_initialize(struct v4l2_subdev *sd)
 	cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
 						 0x03000000, 0x13000000);

-	/* initallize the PLL by toggling sleep bit */
+	/* initialize the PLL by toggling sleep bit */
 	v = cx18_av_read4(cx, CXADEC_HOST_REG1);
 	/* enable sleep mode - register appears to be read only... */
 	cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);