Message ID | 1612629961-11583-3-git-send-email-stefanc@marvell.com |
---|---|
State | New |
Headers | show |
Series | net: mvpp2: Add TX Flow Control support | expand |
> ---------------------------------------------------------------------- > On Sat, 6 Feb 2021 18:45:48 +0200 stefanc@marvell.com wrote: > > From: Konstantin Porotchkin <kostap@marvell.com> > > > > CM3 SRAM address space would be used for Flow Control configuration. > > > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> > > Isn't there are requirement to CC the DT mailing list and Rob on all device > tree patches? Maybe someone can clarify I know it's required when adding > bindings.. I would repost with robh+dt@kernel.org, gregory.clement@bootlin.com and devicetree@vger.kernel.org in CC Thanks, Stefan.
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 9dcf16b..359cf42 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -69,6 +69,8 @@ status = "disabled"; dma-coherent; + cm3-mem = <&CP11X_LABEL(cm3_sram)>; + CP11X_LABEL(eth0): eth0 { interrupts = <39 IRQ_TYPE_LEVEL_HIGH>, <43 IRQ_TYPE_LEVEL_HIGH>, @@ -211,6 +213,14 @@ }; }; + CP11X_LABEL(cm3_sram): cm3@220000 { + compatible = "mmio-sram"; + reg = <0x220000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x220000 0x800>; + }; + CP11X_LABEL(rtc): rtc@284000 { compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>;