@@ -251,6 +251,30 @@ static ssize_t counters_write(struct file *file, const char __user *user_buf,
return ret < 0 ? ret : count;
}
+static void cap_show_by_dw(struct seq_file *s, struct tb_switch *sw,
+ struct tb_port *port, unsigned int cap, unsigned int offset,
+ u8 cap_id, u8 vsec_id, int dwords)
+{
+ int i, ret;
+ u32 data;
+
+ for (i = 0; i < dwords; i++) {
+ if (port)
+ ret = tb_port_read(port, &data, TB_CFG_PORT, cap + offset + i, 1);
+ else
+ ret = tb_sw_read(sw, &data, TB_CFG_SWITCH, cap + offset + i, 1);
+ if (ret) {
+ seq_printf(s, "0x%04x <not accessible>\n", cap + offset);
+ if (dwords - i > 1)
+ seq_printf(s, "0x%04x ...\n", cap + offset + 1);
+ return;
+ }
+
+ seq_printf(s, "0x%04x %4d 0x%02x 0x%02x 0x%08x\n", cap + offset + i,
+ offset + i, cap_id, vsec_id, data);
+ }
+}
+
static void cap_show(struct seq_file *s, struct tb_switch *sw,
struct tb_port *port, unsigned int cap, u8 cap_id,
u8 vsec_id, int length)
@@ -267,10 +291,7 @@ static void cap_show(struct seq_file *s, struct tb_switch *sw,
else
ret = tb_sw_read(sw, data, TB_CFG_SWITCH, cap + offset, dwords);
if (ret) {
- seq_printf(s, "0x%04x <not accessible>\n",
- cap + offset);
- if (dwords > 1)
- seq_printf(s, "0x%04x ...\n", cap + offset + 1);
+ cap_show_by_dw(s, sw, port, cap, offset, cap_id, vsec_id, dwords);
return;
}
@@ -341,15 +362,6 @@ static void port_cap_show(struct tb_port *port, struct seq_file *s,
} else {
length = header.extended_short.length;
vsec_id = header.extended_short.vsec_id;
- /*
- * Ice Lake and Tiger Lake do not implement the
- * full length of the capability, only first 32
- * dwords so hard-code it here.
- */
- if (!vsec_id &&
- (tb_switch_is_ice_lake(port->sw) ||
- tb_switch_is_tiger_lake(port->sw)))
- length = 32;
}
break;
@@ -796,33 +796,6 @@ static inline bool tb_switch_is_titan_ridge(const struct tb_switch *sw)
return false;
}
-static inline bool tb_switch_is_ice_lake(const struct tb_switch *sw)
-{
- if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) {
- switch (sw->config.device_id) {
- case PCI_DEVICE_ID_INTEL_ICL_NHI0:
- case PCI_DEVICE_ID_INTEL_ICL_NHI1:
- return true;
- }
- }
- return false;
-}
-
-static inline bool tb_switch_is_tiger_lake(const struct tb_switch *sw)
-{
- if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL ||
- sw->config.vendor_id == 0x8087) {
- switch (sw->config.device_id) {
- case PCI_DEVICE_ID_INTEL_TGL_NHI0:
- case PCI_DEVICE_ID_INTEL_TGL_NHI1:
- case PCI_DEVICE_ID_INTEL_TGL_H_NHI0:
- case PCI_DEVICE_ID_INTEL_TGL_H_NHI1:
- return true;
- }
- }
- return false;
-}
-
/**
* tb_switch_is_usb4() - Is the switch USB4 compliant
* @sw: Switch to check
There are cases when reading block of dwords in single transaction fail, for several reasons, mostly if HW publish to implement all of the dwords, while actually it doesn't or if some dwords not accessible for read for security reasons. We handle these cases by trying to read the block, dword-by-dword, one dword per transaction, till we get a failure. We drop the not-used functions: tb_switch_is_tiger_lake() and tb_switch_is_ice_lake() Signed-off-by: Gil Fine <gil.fine@intel.com> --- drivers/thunderbolt/debugfs.c | 38 +++++++++++++++++++++++------------ drivers/thunderbolt/tb.h | 27 ------------------------- 2 files changed, 25 insertions(+), 40 deletions(-)