| Message ID | 20210115054736.27769-1-reniuschengl@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL9763E (v2) | expand |
On Fri, 15 Jan 2021 at 06:47, Renius Chen <reniuschengl@gmail.com> wrote: > > GL9763E enters ASPM L1 state after a very short idle in default, > even during a burst of request. So the R/W performance of GL9763E > is low with some platforms, which support ASPM mechanism, due to > entering ASPM L1 state very frequently in R/W process. Set the L1 > entry delay bits in vendor-specific register to 0x3FF to enlarge > the idle period to 260us for improving the R/W performance > of GL9763E. > > Signed-off-by: Renius Chen <reniuschengl@gmail.com> Applied for next, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index c6a107d7c742..fb14f70cb9a0 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -88,6 +88,10 @@ > #define PCIE_GLI_9763E_SCR 0x8E0 > #define GLI_9763E_SCR_AXI_REQ BIT(9) > > +#define PCIE_GLI_9763E_CFG2 0x8A4 > +#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) > +#define GLI_9763E_CFG2_L1DLY_MAX 0x3FF > + > #define PCIE_GLI_9763E_MMC_CTRL 0x960 > #define GLI_9763E_HS400_SLOW BIT(3) > > @@ -792,6 +796,12 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) > value &= ~GLI_9763E_HS400_SLOW; > pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); > > + pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); > + value &= ~GLI_9763E_CFG2_L1DLY; > + /* set ASPM L1 entry delay to 260us */ > + value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX); > + pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); > + > pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); > value &= ~GLI_9763E_VHS_REV; > value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); > -- > 2.27.0 >
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index c6a107d7c742..fb14f70cb9a0 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -88,6 +88,10 @@ #define PCIE_GLI_9763E_SCR 0x8E0 #define GLI_9763E_SCR_AXI_REQ BIT(9) +#define PCIE_GLI_9763E_CFG2 0x8A4 +#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) +#define GLI_9763E_CFG2_L1DLY_MAX 0x3FF + #define PCIE_GLI_9763E_MMC_CTRL 0x960 #define GLI_9763E_HS400_SLOW BIT(3) @@ -792,6 +796,12 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) value &= ~GLI_9763E_HS400_SLOW; pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); + pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); + value &= ~GLI_9763E_CFG2_L1DLY; + /* set ASPM L1 entry delay to 260us */ + value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX); + pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); + pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); value &= ~GLI_9763E_VHS_REV; value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
GL9763E enters ASPM L1 state after a very short idle in default, even during a burst of request. So the R/W performance of GL9763E is low with some platforms, which support ASPM mechanism, due to entering ASPM L1 state very frequently in R/W process. Set the L1 entry delay bits in vendor-specific register to 0x3FF to enlarge the idle period to 260us for improving the R/W performance of GL9763E. Signed-off-by: Renius Chen <reniuschengl@gmail.com> --- drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++ 1 file changed, 10 insertions(+)