| Message ID | 20210107183907.6545-6-s-anna@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add R5F nodes on TI K3 J7200 SoCs | expand |
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 69db8e77f659..a988e2ab2ba1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -73,6 +73,12 @@ main_r5fss0_core1_memory_region: r5f-memory@a3100000 { reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a4000000 { + reg = <0x00 0xa4000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; };
Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS on the TI J7200 EVM boards. 8 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. NOTE: The J7200 SoCs have no DSPs and one less R5F cluster compared to J721E SoCs. So, while the carveout memories reserved for the R5F clusters present on the SoC match to those on J721E, the overall memory map reserved for firmwares is quite different. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)