| Message ID | 1610129731-4875-1-git-send-email-akhilpo@codeaurora.org |
|---|---|
| State | Accepted |
| Commit | fe7952c629daec6fb71f55376cb2ed543fde3186 |
| Headers | show |
| Series | [v4,1/2] drm/msm: Add speed-bin support to a618 gpu | expand |
On Fri, Jan 08, 2021 at 11:45:30PM +0530, Akhil P Oommen wrote: > Some GPUs support different max frequencies depending on the platform. > To identify the correct variant, we should check the gpu speedbin > fuse value. Add support for this speedbin detection to a6xx family > along with the required fuse details for a618 gpu. Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> > Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> > --- > Changes from v2: > 1. Made the changes a6xx specific to save space. > Changes from v1: > 1. Added the changes to support a618 sku to the series. > 2. Avoid failing probe in case of an unsupported sku. (Rob) > Changes from v3: > 1. Replace a618_speedbins[] with a function. (Jordan) > > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 + > 2 files changed, 85 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 1306618..499d134 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -10,6 +10,7 @@ > > #include <linux/bitfield.h> > #include <linux/devfreq.h> > +#include <linux/nvmem-consumer.h> > #include <linux/soc/qcom/llcc-qcom.h> > > #define GPU_PAS_ID 13 > @@ -1208,6 +1209,10 @@ static void a6xx_destroy(struct msm_gpu *gpu) > a6xx_gmu_remove(a6xx_gpu); > > adreno_gpu_cleanup(adreno_gpu); > + > + if (a6xx_gpu->opp_table) > + dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table); > + > kfree(a6xx_gpu); > } > > @@ -1264,6 +1269,78 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); > } > > +static u32 a618_get_speed_bin(u32 fuse) > +{ > + if (fuse == 0) > + return 0; > + else if (fuse == 169) > + return 1; > + else if (fuse == 174) > + return 2; > + > + return UINT_MAX; > +} > + > +static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) > +{ > + u32 val = UINT_MAX; > + > + if (revn == 618) > + val = a618_get_speed_bin(fuse); > + > + if (val == UINT_MAX) { > + DRM_DEV_ERROR(dev, > + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", > + fuse); > + return UINT_MAX; > + } > + > + return (1 << val); > +} > + > +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, > + u32 revn) > +{ > + struct opp_table *opp_table; > + struct nvmem_cell *cell; > + u32 supp_hw = UINT_MAX; > + void *buf; > + > + cell = nvmem_cell_get(dev, "speed_bin"); > + /* > + * -ENOENT means that the platform doesn't support speedbin which is > + * fine > + */ > + if (PTR_ERR(cell) == -ENOENT) > + return 0; > + else if (IS_ERR(cell)) { > + DRM_DEV_ERROR(dev, > + "failed to read speed-bin. Some OPPs may not be supported by hardware"); > + goto done; > + } > + > + buf = nvmem_cell_read(cell, NULL); > + if (IS_ERR(buf)) { > + nvmem_cell_put(cell); > + DRM_DEV_ERROR(dev, > + "failed to read speed-bin. Some OPPs may not be supported by hardware"); > + goto done; > + } > + > + supp_hw = fuse_to_supp_hw(dev, revn, *((u32 *) buf)); > + > + kfree(buf); > + nvmem_cell_put(cell); > + > +done: > + opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1); > + if (IS_ERR(opp_table)) > + return PTR_ERR(opp_table); > + > + a6xx_gpu->opp_table = opp_table; > + return 0; > +} > + > static const struct adreno_gpu_funcs funcs = { > .base = { > .get_param = adreno_get_param, > @@ -1325,6 +1402,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > > a6xx_llc_slices_init(pdev, a6xx_gpu); > > + ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn); > + if (ret) { > + a6xx_destroy(&(a6xx_gpu->base.base)); > + return ERR_PTR(ret); > + } > + > ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); > if (ret) { > a6xx_destroy(&(a6xx_gpu->base.base)); > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index e793d32..ce0610c 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -33,6 +33,8 @@ struct a6xx_gpu { > void *llc_slice; > void *htw_llc_slice; > bool have_mmu500; > + > + struct opp_table *opp_table; > }; > > #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base) > -- > 2.7.4 >
On 2/3/2021 4:22 AM, Bjorn Andersson wrote: > On Fri 08 Jan 12:15 CST 2021, Akhil P Oommen wrote: > > Please align the $subject prefix with other changes in the same file. > I fixed it up while picking up the patch this time. > Will take of this in future. Thanks, Bjorn. -Akhil. > Regards, > Bjorn > >> Add support for gpu fuse to help identify the supported opps. >> >> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> index 6678f1e..8cae3eb 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi >> @@ -675,6 +675,11 @@ >> reg = <0x25b 0x1>; >> bits = <1 3>; >> }; >> + >> + gpu_speed_bin: gpu_speed_bin@1d2 { >> + reg = <0x1d2 0x2>; >> + bits = <5 8>; >> + }; >> }; >> >> sdhc_1: sdhci@7c4000 { >> @@ -1907,52 +1912,69 @@ >> operating-points-v2 = <&gpu_opp_table>; >> qcom,gmu = <&gmu>; >> >> + nvmem-cells = <&gpu_speed_bin>; >> + nvmem-cell-names = "speed_bin"; >> + >> interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; >> interconnect-names = "gfx-mem"; >> >> gpu_opp_table: opp-table { >> compatible = "operating-points-v2"; >> >> + opp-825000000 { >> + opp-hz = /bits/ 64 <825000000>; >> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; >> + opp-peak-kBps = <8532000>; >> + opp-supported-hw = <0x04>; >> + }; >> + >> opp-800000000 { >> opp-hz = /bits/ 64 <800000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; >> opp-peak-kBps = <8532000>; >> + opp-supported-hw = <0x07>; >> }; >> >> opp-650000000 { >> opp-hz = /bits/ 64 <650000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; >> opp-peak-kBps = <7216000>; >> + opp-supported-hw = <0x07>; >> }; >> >> opp-565000000 { >> opp-hz = /bits/ 64 <565000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_NOM>; >> opp-peak-kBps = <5412000>; >> + opp-supported-hw = <0x07>; >> }; >> >> opp-430000000 { >> opp-hz = /bits/ 64 <430000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; >> opp-peak-kBps = <5412000>; >> + opp-supported-hw = <0x07>; >> }; >> >> opp-355000000 { >> opp-hz = /bits/ 64 <355000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_SVS>; >> opp-peak-kBps = <3072000>; >> + opp-supported-hw = <0x07>; >> }; >> >> opp-267000000 { >> opp-hz = /bits/ 64 <267000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; >> opp-peak-kBps = <3072000>; >> + opp-supported-hw = <0x07>; >> }; >> >> opp-180000000 { >> opp-hz = /bits/ 64 <180000000>; >> opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; >> opp-peak-kBps = <1804000>; >> + opp-supported-hw = <0x07>; >> }; >> }; >> }; >> -- >> 2.7.4 >> > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel >
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1306618..499d134 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,7 @@ #include <linux/bitfield.h> #include <linux/devfreq.h> +#include <linux/nvmem-consumer.h> #include <linux/soc/qcom/llcc-qcom.h> #define GPU_PAS_ID 13 @@ -1208,6 +1209,10 @@ static void a6xx_destroy(struct msm_gpu *gpu) a6xx_gmu_remove(a6xx_gpu); adreno_gpu_cleanup(adreno_gpu); + + if (a6xx_gpu->opp_table) + dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table); + kfree(a6xx_gpu); } @@ -1264,6 +1269,78 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); } +static u32 a618_get_speed_bin(u32 fuse) +{ + if (fuse == 0) + return 0; + else if (fuse == 169) + return 1; + else if (fuse == 174) + return 2; + + return UINT_MAX; +} + +static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse) +{ + u32 val = UINT_MAX; + + if (revn == 618) + val = a618_get_speed_bin(fuse); + + if (val == UINT_MAX) { + DRM_DEV_ERROR(dev, + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", + fuse); + return UINT_MAX; + } + + return (1 << val); +} + +static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu, + u32 revn) +{ + struct opp_table *opp_table; + struct nvmem_cell *cell; + u32 supp_hw = UINT_MAX; + void *buf; + + cell = nvmem_cell_get(dev, "speed_bin"); + /* + * -ENOENT means that the platform doesn't support speedbin which is + * fine + */ + if (PTR_ERR(cell) == -ENOENT) + return 0; + else if (IS_ERR(cell)) { + DRM_DEV_ERROR(dev, + "failed to read speed-bin. Some OPPs may not be supported by hardware"); + goto done; + } + + buf = nvmem_cell_read(cell, NULL); + if (IS_ERR(buf)) { + nvmem_cell_put(cell); + DRM_DEV_ERROR(dev, + "failed to read speed-bin. Some OPPs may not be supported by hardware"); + goto done; + } + + supp_hw = fuse_to_supp_hw(dev, revn, *((u32 *) buf)); + + kfree(buf); + nvmem_cell_put(cell); + +done: + opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1); + if (IS_ERR(opp_table)) + return PTR_ERR(opp_table); + + a6xx_gpu->opp_table = opp_table; + return 0; +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, @@ -1325,6 +1402,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu); + ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info->revn); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index e793d32..ce0610c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -33,6 +33,8 @@ struct a6xx_gpu { void *llc_slice; void *htw_llc_slice; bool have_mmu500; + + struct opp_table *opp_table; }; #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
Some GPUs support different max frequencies depending on the platform. To identify the correct variant, we should check the gpu speedbin fuse value. Add support for this speedbin detection to a6xx family along with the required fuse details for a618 gpu. Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> --- Changes from v2: 1. Made the changes a6xx specific to save space. Changes from v1: 1. Added the changes to support a618 sku to the series. 2. Avoid failing probe in case of an unsupported sku. (Rob) Changes from v3: 1. Replace a618_speedbins[] with a function. (Jordan) drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 83 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 + 2 files changed, 85 insertions(+)