@@ -172,7 +172,7 @@ void gic_unmask_irq(struct irq_data *d)
raw_spin_unlock(&irq_controller_lock);
}
-void gic_eoi_irq(struct irq_data *d)
+static void gic_eoi_irq(struct irq_data *d)
{
if (gic_arch_extn.irq_eoi) {
raw_spin_lock(&irq_controller_lock);
@@ -183,7 +183,7 @@ void gic_eoi_irq(struct irq_data *d)
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
-int gic_set_type(struct irq_data *d, unsigned int type)
+static int gic_set_type(struct irq_data *d, unsigned int type)
{
void __iomem *base = gic_dist_base(d);
unsigned int gicirq = gic_irq(d);
@@ -207,7 +207,7 @@ int gic_set_type(struct irq_data *d, unsigned int type)
return 0;
}
-int gic_retrigger(struct irq_data *d)
+static int gic_retrigger(struct irq_data *d)
{
if (gic_arch_extn.irq_retrigger)
return gic_arch_extn.irq_retrigger(d);
@@ -217,7 +217,7 @@ int gic_retrigger(struct irq_data *d)
}
#ifdef CONFIG_SMP
-int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
+static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
bool force)
{
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
@@ -244,7 +244,7 @@ int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
#endif
#ifdef CONFIG_PM
-int gic_set_wake(struct irq_data *d, unsigned int on)
+static int gic_set_wake(struct irq_data *d, unsigned int on)
{
int ret = -ENXIO;
@@ -50,18 +50,5 @@ int _gic_of_init(struct device_node *node,
void gic_mask_irq(struct irq_data *d);
void gic_unmask_irq(struct irq_data *d);
-void gic_eoi_irq(struct irq_data *d);
-int gic_set_type(struct irq_data *d, unsigned int type);
-int gic_retrigger(struct irq_data *d);
-
-#ifdef CONFIG_SMP
-int gic_set_affinity(struct irq_data *d,
- const struct cpumask *mask_val,
- bool force);
-#endif
-
-#ifdef CONFIG_PM
-int gic_set_wake(struct irq_data *d, unsigned int on);
-#endif
#endif /* _IRQ_GIC_H_ */