| Message ID | 20201223060204.576856-10-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: backend constraints cleanup | expand |
On Tue, Dec 22, 2020 at 10:13 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target-constr.h | 24 +++++++++++++++++++++ > tcg/riscv/tcg-target.h | 1 + > tcg/riscv/tcg-target.c.inc | 39 ----------------------------------- > 3 files changed, 25 insertions(+), 39 deletions(-) > create mode 100644 tcg/riscv/tcg-target-constr.h > > diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h > new file mode 100644 > index 0000000000..5daf2e6a5b > --- /dev/null > +++ b/tcg/riscv/tcg-target-constr.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * RISC-V target-specific operand constaints. > + * Copyright (c) 2020 Linaro > + */ > + > +#define ALL_GENERAL_REGS 0xffffffffu > + > +#ifdef CONFIG_SOFTMMU > +#define ALL_QLDST_REGS \ > + (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \ > + (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \ > + (1 << TCG_REG_A5))) > +#else > +#define ALL_QLDST_REGS ALL_GENERAL_REGS > +#endif > + > +REGS('r', ALL_GENERAL_REGS) > +REGS('L', ALL_QLDST_REGS) > + > +CONST('I', TCG_CT_CONST_S12) > +CONST('N', TCG_CT_CONST_N12) > +CONST('M', TCG_CT_CONST_M12) > +CONST('Z', TCG_CT_CONST_ZERO) > diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h > index 032439d806..ff8ff43a46 100644 > --- a/tcg/riscv/tcg-target.h > +++ b/tcg/riscv/tcg-target.h > @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); > #define TCG_TARGET_NEED_POOL_LABELS > > #define TCG_TARGET_HAS_MEMORY_BSWAP 0 > +#define TCG_TARGET_CONSTR_H > > #endif > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index d536f3ccc1..33047c1951 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -131,45 +131,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) > } > } > > -/* parse target specific constraints */ > -static const char *target_parse_constraint(TCGArgConstraint *ct, > - const char *ct_str, TCGType type) > -{ > - switch (*ct_str++) { > - case 'r': > - ct->regs = 0xffffffff; > - break; > - case 'L': > - /* qemu_ld/qemu_st constraint */ > - ct->regs = 0xffffffff; > - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ > -#if defined(CONFIG_SOFTMMU) > - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); > - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); > - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); > - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); > - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); > -#endif > - break; > - case 'I': > - ct->ct |= TCG_CT_CONST_S12; > - break; > - case 'N': > - ct->ct |= TCG_CT_CONST_N12; > - break; > - case 'M': > - ct->ct |= TCG_CT_CONST_M12; > - break; > - case 'Z': > - /* we can use a zero immediate as a zero register argument. */ > - ct->ct |= TCG_CT_CONST_ZERO; > - break; > - default: > - return NULL; > - } > - return ct_str; > -} > - > /* test if a constant matches the constraint */ > static int tcg_target_const_match(tcg_target_long val, TCGType type, > const TCGArgConstraint *arg_ct) > -- > 2.25.1 > >
diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h new file mode 100644 index 0000000000..5daf2e6a5b --- /dev/null +++ b/tcg/riscv/tcg-target-constr.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: MIT */ +/* + * RISC-V target-specific operand constaints. + * Copyright (c) 2020 Linaro + */ + +#define ALL_GENERAL_REGS 0xffffffffu + +#ifdef CONFIG_SOFTMMU +#define ALL_QLDST_REGS \ + (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \ + (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \ + (1 << TCG_REG_A5))) +#else +#define ALL_QLDST_REGS ALL_GENERAL_REGS +#endif + +REGS('r', ALL_GENERAL_REGS) +REGS('L', ALL_QLDST_REGS) + +CONST('I', TCG_CT_CONST_S12) +CONST('N', TCG_CT_CONST_N12) +CONST('M', TCG_CT_CONST_M12) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 032439d806..ff8ff43a46 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -175,5 +175,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS #define TCG_TARGET_HAS_MEMORY_BSWAP 0 +#define TCG_TARGET_CONSTR_H #endif diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d536f3ccc1..33047c1951 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -131,45 +131,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) } } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->regs = 0xffffffff; - break; - case 'L': - /* qemu_ld/qemu_st constraint */ - ct->regs = 0xffffffff; - /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ -#if defined(CONFIG_SOFTMMU) - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); - tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); -#endif - break; - case 'I': - ct->ct |= TCG_CT_CONST_S12; - break; - case 'N': - ct->ct |= TCG_CT_CONST_N12; - break; - case 'M': - ct->ct |= TCG_CT_CONST_M12; - break; - case 'Z': - /* we can use a zero immediate as a zero register argument. */ - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target-constr.h | 24 +++++++++++++++++++++ tcg/riscv/tcg-target.h | 1 + tcg/riscv/tcg-target.c.inc | 39 ----------------------------------- 3 files changed, 25 insertions(+), 39 deletions(-) create mode 100644 tcg/riscv/tcg-target-constr.h -- 2.25.1