@@ -49,8 +49,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
uintptr_t next_tb;
uint8_t *tb_ptr = itb->tc_ptr;
- qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
- itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
+ qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
+ "Trace %p [" TARGET_FMT_lx "] %s\n",
+ itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
#if defined(DEBUG_DISAS)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
@@ -76,10 +77,10 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
*/
CPUClass *cc = CPU_GET_CLASS(cpu);
TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
- qemu_log_mask(CPU_LOG_EXEC,
- "Abandoned execution of TB chain before %p ["
- TARGET_FMT_lx "] %s\n",
- itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
+ qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
+ "Abandoned execution of TB chain before %p ["
+ TARGET_FMT_lx "] %s\n",
+ itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
if (cc->synchronize_from_tb) {
cc->synchronize_from_tb(cpu, tb);
} else {
@@ -297,9 +297,11 @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
{
/* NOTE: this test is only needed for thread safety */
if (!tb->jmp_next[n]) {
- qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p [" TARGET_FMT_lx
- "] index %d -> %p [" TARGET_FMT_lx "]\n",
- tb->tc_ptr, tb->pc, n, tb_next->tc_ptr, tb_next->pc);
+ qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
+ "Linking TBs %p [" TARGET_FMT_lx
+ "] index %d -> %p [" TARGET_FMT_lx "]\n",
+ tb->tc_ptr, tb->pc, n,
+ tb_next->tc_ptr, tb_next->pc);
/* patch the native jump address */
tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
@@ -76,6 +76,21 @@ qemu_log_vprintf(const char *fmt, va_list va)
} \
} while (0)
+/* log only if a bit is set on the current loglevel mask
+ * and we are in the address range we care about:
+ * @mask: bit to check in the mask
+ * @addr: address to check in dfilter
+ * @fmt: printf-style format string
+ * @args: optional arguments for format string
+ */
+#define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \
+ do { \
+ if (unlikely(qemu_loglevel_mask(MASK)) && \
+ qemu_log_in_addr_range(ADDR)) { \
+ qemu_log(FMT, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
/* Special cases: */
/* cpu_dump_state() logging functions: */
@@ -2427,7 +2427,8 @@ static inline int tcg_gen_code_common(TCGContext *s, TranslationBlock *tb,
g_assert(tb->tc_size == 0 || search_pc > 0);
#ifdef DEBUG_DISAS
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
+ && qemu_log_in_addr_range(tb->pc))) {
qemu_log("OP:\n");
tcg_dump_ops(s);
qemu_log("\n");
@@ -2455,7 +2456,8 @@ static inline int tcg_gen_code_common(TCGContext *s, TranslationBlock *tb,
#endif
#ifdef DEBUG_DISAS
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
+ && qemu_log_in_addr_range(tb->pc))) {
qemu_log("OP after optimization and liveness analysis:\n");
tcg_dump_ops(s);
qemu_log("\n");
@@ -2478,11 +2480,6 @@ static inline int tcg_gen_code_common(TCGContext *s, TranslationBlock *tb,
tcg_table_op_count[opc]++;
#endif
def = &tcg_op_defs[opc];
-#if 0
- printf("%s: %d %d %d\n", def->name,
- def->nb_oargs, def->nb_iargs, def->nb_cargs);
- // dump_regs(s);
-#endif
switch(opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
@@ -199,7 +199,8 @@ void cpu_gen_code(CPUArchState *env, TranslationBlock *tb)
tb_write_perfmap(tb->tc_ptr, tb->tc_size, tb->pc);
#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) &&
+ qemu_log_in_addr_range(tb->pc)) {
qemu_log("OUT: [size=%d]\n", tb->tc_size);
log_disas(tb->tc_ptr, tb->tc_size);
qemu_log("\n");
This ensures the code generation debug code will honour -dfilter if set. For the "exec" tracing I've added a new inline macro for efficiency's sake. I've not touched CPU_LOG_TB_OP as this is buried in each individual target. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> ---- v2 - checkpatch updates - add qemu_log_mask_and_addr macro for inline dump for traces - re-base on re-factored tcg layout - include new Trace & Link lines