| Message ID | 20201208143239.1129168-1-daniel.thompson@linaro.org |
|---|---|
| State | Accepted |
| Commit | 9aaf9bb7943be36ebde177a297ff54824961408d |
| Headers | show |
| Series | ARM: Kconfig: Select ARCH_HAVE_NMI_SAFE_CMPXCHG where possible | expand |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 002e0cf025f59..fd434c5958b62 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -24,6 +24,7 @@ config ARM select ARCH_HAS_TEARDOWN_DMA_OPS if MMU select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAVE_CUSTOM_GPIO_H + select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC select ARCH_MIGHT_HAVE_PC_PARPORT
Currently ARCH_HAVE_NMI_SAFE_CMPXCHG is not set on Arm systems and this makes it impossible to enable features such as ftrace histogram triggers on Arm platforms. Most Arm systems are NMI safe simply because there is no NMI but this isn't universally true meaning we cannot set ARCH_HAVE_NMI_SAFE_CMPXCHG for all Arm devices. However the load/store exclusive implementation of cmpxchg is NMI-safe and this implementation is used ARMv6k and later. Let's select ARCH_HAVE_NMI_SAFE_CMPXCHG for these systems. Note that ARMv6 uses load/store exclusive for 32-bit cmpxchg but relies on interrupt masking for 8- and 16-bit operations. This patch is conservative and does not change behaviour for CPU_V6. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) base-commit: 0477e92881850d44910a7e94fc2c46f96faa131f -- 2.28.0