[05/38] ccs-pll: Remove parallel bus support

Message ID	20201202180641.17401-6-sakari.ailus@linux.intel.com
State	Accepted
Commit	6aadbff9d459d4e4ebaedf19d50b0f057574f756
Headers	show Return-Path: <linux-media-owner@kernel.org> From: Sakari Ailus <sakari.ailus@linux.intel.com> To: linux-media@vger.kernel.org Cc: mchehab@kernel.org Subject: [PATCH 05/38] ccs-pll: Remove parallel bus support Date: Wed, 2 Dec 2020 20:06:08 +0200 Message-Id: <20201202180641.17401-6-sakari.ailus@linux.intel.com> In-Reply-To: <20201202180641.17401-1-sakari.ailus@linux.intel.com> References: <20201202180641.17401-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Support additional CCS PLL features, C-PHY \| expand [00/38] Support additional CCS PLL features, C-PHY [02/38] ccs-pll: Split limits and PLL configuration into front and back parts [04/38] ccs-pll: End search if there are no better values available [05/38] ccs-pll: Remove parallel bus support [06/38] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY [10/38] ccs-pll: Begin calculation from OP system clock frequency [12/38] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search [16/38] ccs-pll: Add support for lane speed model [17/38] ccs: Add support for lane speed model [19/38] ccs-pll: Add support for extended input PLL clock divider [22/38] ccs-pll: Add sanity checks [23/38] ccs-pll: Add C-PHY support [24/38] ccs-pll: Split off VT subtree calculation [27/38] ccs-pll: Print relevant information on PLL tree [29/38] ccs-pll: Make VT divisors 16-bit [30/38] ccs-pll: Fix VT post-PLL divisor calculation [32/38] ccs-pll: Add trivial dual PLL support [34/38] ccs-pll: Add support for DDR OP system and pixel clocks [36/38] ccs: Print written register values [37/38] ccs-pll: Print pixel rates

Message ID

20201202180641.17401-6-sakari.ailus@linux.intel.com

State

Accepted

Commit

6aadbff9d459d4e4ebaedf19d50b0f057574f756

Headers

From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: mchehab@kernel.org
Subject: [PATCH 05/38] ccs-pll: Remove parallel bus support
Date: Wed,  2 Dec 2020 20:06:08 +0200
Message-Id: <20201202180641.17401-6-sakari.ailus@linux.intel.com>
In-Reply-To: <20201202180641.17401-1-sakari.ailus@linux.intel.com>
References: <20201202180641.17401-1-sakari.ailus@linux.intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Support additional CCS PLL features, C-PHY | expand

Commit Message

Sakari Ailus Dec. 2, 2020, 6:06 p.m. UTC

The parallel bus PLL calculation has no users. Remove it.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 drivers/media/i2c/ccs-pll.c |  5 -----
 drivers/media/i2c/ccs-pll.h | 14 ++++----------
 2 files changed, 4 insertions(+), 15 deletions(-)

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 22e29127804a..da97a2b91717 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -435,11 +435,6 @@  int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 		op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * 2
 			* (pll->csi2.lanes / lane_op_clock_ratio);
 		break;
-	case CCS_PLL_BUS_TYPE_PARALLEL:
-		op_pll_fr->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
-			/ DIV_ROUND_UP(pll->bits_per_pixel,
-				       pll->parallel.bus_width);
-		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 03b1d8d11423..578c9272688a 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -13,8 +13,7 @@ 
 #define CCS_PLL_H
 
 /* CSI-2 or CCP-2 */
-#define CCS_PLL_BUS_TYPE_CSI2				0x00
-#define CCS_PLL_BUS_TYPE_PARALLEL				0x01
+#define CCS_PLL_BUS_TYPE_CSI2					0x00
 
 /* op pix clock is for all lanes in total normally */
 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE			(1 << 0)
@@ -37,14 +36,9 @@  struct ccs_pll_branch_bk {
 struct ccs_pll {
 	/* input values */
 	uint8_t bus_type;
-	union {
-		struct {
-			uint8_t lanes;
-		} csi2;
-		struct {
-			uint8_t bus_width;
-		} parallel;
-	};
+	struct {
+		uint8_t lanes;
+	} csi2;
 	unsigned long flags;
 	uint8_t binning_horizontal;
 	uint8_t binning_vertical;

[05/38] ccs-pll: Remove parallel bus support

Commit Message

Patch