| Message ID | 1405355950-6461-5-git-send-email-ian.campbell@citrix.com |
|---|---|
| State | Accepted |
| Commit | f1870804e58565399cd770e93f62e7ce57cd5231 |
| Headers | show |
Hi Ian, On 14/07/14 17:39, Ian Campbell wrote: > Otherwise a stale TLB entry can shadow the fixmap/UART or DTB mapping > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Good catch! I guess this could also happen on Xen 4.4. I would consider to backport it :) Acked-by: Julien Grall <julien.grall@linaro.org> Regards,
On Wed, 2014-07-16 at 19:11 +0100, Julien Grall wrote: > Hi Ian, > > On 14/07/14 17:39, Ian Campbell wrote: > > Otherwise a stale TLB entry can shadow the fixmap/UART or DTB mapping > > > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> > > Good catch! I guess this could also happen on Xen 4.4. I would consider > to backport it :) I noticed when moving the PRINT(- Ready -) to right after x32 (for debug purposes) was reloaded with the UART address failed. I've added this to my backports list. > Acked-by: Julien Grall <julien.grall@linaro.org> Cheers. Ian.
On Wed, 2014-07-16 at 19:11 +0100, Julien Grall wrote: > Hi Ian, > > On 14/07/14 17:39, Ian Campbell wrote: > > Otherwise a stale TLB entry can shadow the fixmap/UART or DTB mapping > > > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> > > Good catch! I guess this could also happen on Xen 4.4. I would consider > to backport it :) > > Acked-by: Julien Grall <julien.grall@linaro.org> Applied just this one patch from the series, thanks. Ian.
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 348ca7d..a36c8fc 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -398,9 +398,20 @@ paging: ldr r4, =BOOT_FDT_VIRT_START mov r4, r4, lsr #(SECOND_SHIFT - 3) /* Slot for BOOT_FDT_VIRT_START */ strd r2, r3, [r1, r4] /* Map it in the early fdt slot */ - dsb 1: + /* + * Flush the TLB in case the 1:1 mapping happens to clash with + * the virtual addresses used by the fixmap or DTB. + */ + dsb /* Ensure any page table updates made above + * have occurred. */ + + isb + mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */ + dsb /* Ensure completion of TLB flush */ + isb + PRINT("- Ready -\r\n") /* The boot CPU should go straight into C now */ diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S index 7152d9c..a50192e 100644 --- a/xen/arch/arm/arm64/head.S +++ b/xen/arch/arm/arm64/head.S @@ -432,9 +432,20 @@ paging: ldr x1, =BOOT_FDT_VIRT_START lsr x1, x1, #(SECOND_SHIFT - 3) /* x4 := Slot for BOOT_FDT_VIRT_START */ str x2, [x4, x1] /* Map it in the early fdt slot */ - dsb sy 1: + /* + * Flush the TLB in case the 1:1 mapping happens to clash with + * the virtual addresses used by the fixmap or DTB. + */ + dsb sy /* Ensure any page table updates made above + * have occurred. */ + + isb + tlbi alle2 + dsb sy /* Ensure completion of TLB flush */ + isb + PRINT("- Ready -\r\n") /* The boot CPU should go straight into C now */
Otherwise a stale TLB entry can shadow the fixmap/UART or DTB mapping Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- xen/arch/arm/arm32/head.S | 13 ++++++++++++- xen/arch/arm/arm64/head.S | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-)