diff mbox series

[2/2] perf/imx_ddr: Add system PMU identifier for userspace

Message ID 20201128053627.7971-3-qiangqing.zhang@nxp.com
State Superseded
Headers show
Series perf/imx_ddr: Add sysfs identifier file | expand

Commit Message

Joakim Zhang Nov. 28, 2020, 5:36 a.m. UTC
The DDR Perf for i.MX8 is a system PMU whose AXI ID would different from
SoC to SoC. Need expose system PMU identifier for userspace which refer
to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.

Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
 drivers/perf/fsl_imx8_ddr_perf.c | 42 ++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

Comments

John Garry Nov. 30, 2020, 9:46 a.m. UTC | #1
On 28/11/2020 05:36, Joakim Zhang wrote:
> The DDR Perf for i.MX8 is a system PMU whose AXI ID would different from

> SoC to SoC. Need expose system PMU identifier for userspace which refer

> to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.

> 

> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

> ---

>   drivers/perf/fsl_imx8_ddr_perf.c | 42 ++++++++++++++++++++++++++++++++

>   1 file changed, 42 insertions(+)

> 

> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c

> index 4f063fb1c6b4..3517d2fb1469 100644

> --- a/drivers/perf/fsl_imx8_ddr_perf.c

> +++ b/drivers/perf/fsl_imx8_ddr_perf.c

> @@ -50,6 +50,7 @@ static DEFINE_IDA(ddr_ida);

>   

>   struct fsl_ddr_devtype_data {

>   	unsigned int quirks;    /* quirks needed for different DDR Perf core */

> +	const char *identifier;	/* system PMU identifier for userspace */


so if this is not set, then what does the sysfs identifier file show?

It seems to be not set for "fsl,imx8-ddr-pmu" or "fsl,imx8m-ddr-pmu" 
matching.

Maybe it's better do like I did for SMMU PMCG, and not show the file if 
not set.

Thanks,
John

>   };

>   

>   static const struct fsl_ddr_devtype_data imx8_devtype_data;

> @@ -58,13 +59,32 @@ static const struct fsl_ddr_devtype_data imx8m_devtype_data = {

>   	.quirks = DDR_CAP_AXI_ID_FILTER,

>   };

>   

> +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {

> +	.quirks = DDR_CAP_AXI_ID_FILTER,

> +	.identifier = "i.MX8MQ",

> +};

> +

> +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {

> +	.quirks = DDR_CAP_AXI_ID_FILTER,

> +	.identifier = "i.MX8MM",

> +};

> +

> +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {

> +	.quirks = DDR_CAP_AXI_ID_FILTER,

> +	.identifier = "i.MX8MN",

> +};

> +

>   static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {

>   	.quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,

> +	.identifier = "i.MX8MP",

>   };

>   

>   static const struct of_device_id imx_ddr_pmu_dt_ids[] = {

>   	{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},

>   	{ .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},

> +	{ .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},

> +	{ .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},

> +	{ .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},

>   	{ .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},

>   	{ /* sentinel */ }

>   };

> @@ -84,6 +104,27 @@ struct ddr_pmu {

>   	int id;

>   };

>   

> +static ssize_t ddr_perf_identifier_show(struct device *dev,

> +					struct device_attribute *attr,

> +					char *page)

> +{

> +	struct ddr_pmu *pmu = dev_get_drvdata(dev);

> +

> +	return sprintf(page, "%s\n", pmu->devtype_data->identifier);

> +}

> +

> +static struct device_attribute ddr_perf_identifier_attr =

> +	__ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);

> +

> +static struct attribute *ddr_perf_identifier_attrs[] = {

> +	&ddr_perf_identifier_attr.attr,

> +	NULL,

> +};

> +

> +static struct attribute_group ddr_perf_identifier_attr_group = {

> +	.attrs = ddr_perf_identifier_attrs,

> +};

> +

>   enum ddr_perf_filter_capabilities {

>   	PERF_CAP_AXI_ID_FILTER = 0,

>   	PERF_CAP_AXI_ID_FILTER_ENHANCED,

> @@ -237,6 +278,7 @@ static const struct attribute_group *attr_groups[] = {

>   	&ddr_perf_format_attr_group,

>   	&ddr_perf_cpumask_attr_group,

>   	&ddr_perf_filter_cap_attr_group,

> +	&ddr_perf_identifier_attr_group,

>   	NULL,

>   };

>   

>
Joakim Zhang Nov. 30, 2020, 10:55 a.m. UTC | #2
> -----Original Message-----

> From: John Garry <john.garry@huawei.com>

> Sent: 2020年11月30日 17:46

> To: Joakim Zhang <qiangqing.zhang@nxp.com>; will@kernel.org;

> robh+dt@kernel.org

> Cc: devicetree@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>; Frank Li

> <frank.li@nxp.com>

> Subject: Re: [PATCH 2/2] perf/imx_ddr: Add system PMU identifier for

> userspace

> 

> On 28/11/2020 05:36, Joakim Zhang wrote:

> > The DDR Perf for i.MX8 is a system PMU whose AXI ID would different

> > from SoC to SoC. Need expose system PMU identifier for userspace which

> > refer to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.

> >

> > Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>

> > ---

> >   drivers/perf/fsl_imx8_ddr_perf.c | 42

> ++++++++++++++++++++++++++++++++

> >   1 file changed, 42 insertions(+)

> >

> > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c

> > b/drivers/perf/fsl_imx8_ddr_perf.c

> > index 4f063fb1c6b4..3517d2fb1469 100644

> > --- a/drivers/perf/fsl_imx8_ddr_perf.c

> > +++ b/drivers/perf/fsl_imx8_ddr_perf.c

> > @@ -50,6 +50,7 @@ static DEFINE_IDA(ddr_ida);

> >

> >   struct fsl_ddr_devtype_data {

> >   	unsigned int quirks;    /* quirks needed for different DDR Perf core

> */

> > +	const char *identifier;	/* system PMU identifier for userspace */

> 

> so if this is not set, then what does the sysfs identifier file show?


Seems to be (null).

> It seems to be not set for "fsl,imx8-ddr-pmu" or "fsl,imx8m-ddr-pmu"

> matching.

> 

> Maybe it's better do like I did for SMMU PMCG, and not show the file if not set.


OK, I will improve it. Thanks.

Best Regards,
Joakim Zhang
> Thanks,

> John

> 

> >   };

> >

> >   static const struct fsl_ddr_devtype_data imx8_devtype_data; @@

> > -58,13 +59,32 @@ static const struct fsl_ddr_devtype_data

> imx8m_devtype_data = {

> >   	.quirks = DDR_CAP_AXI_ID_FILTER,

> >   };

> >

> > +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {

> > +	.quirks = DDR_CAP_AXI_ID_FILTER,

> > +	.identifier = "i.MX8MQ",

> > +};

> > +

> > +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {

> > +	.quirks = DDR_CAP_AXI_ID_FILTER,

> > +	.identifier = "i.MX8MM",

> > +};

> > +

> > +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {

> > +	.quirks = DDR_CAP_AXI_ID_FILTER,

> > +	.identifier = "i.MX8MN",

> > +};

> > +

> >   static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {

> >   	.quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,

> > +	.identifier = "i.MX8MP",

> >   };

> >

> >   static const struct of_device_id imx_ddr_pmu_dt_ids[] = {

> >   	{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},

> >   	{ .compatible = "fsl,imx8m-ddr-pmu", .data =

> &imx8m_devtype_data},

> > +	{ .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},

> > +	{ .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},

> > +	{ .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},

> >   	{ .compatible = "fsl,imx8mp-ddr-pmu", .data =

> &imx8mp_devtype_data},

> >   	{ /* sentinel */ }

> >   };

> > @@ -84,6 +104,27 @@ struct ddr_pmu {

> >   	int id;

> >   };

> >

> > +static ssize_t ddr_perf_identifier_show(struct device *dev,

> > +					struct device_attribute *attr,

> > +					char *page)

> > +{

> > +	struct ddr_pmu *pmu = dev_get_drvdata(dev);

> > +

> > +	return sprintf(page, "%s\n", pmu->devtype_data->identifier); }

> > +

> > +static struct device_attribute ddr_perf_identifier_attr =

> > +	__ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);

> > +

> > +static struct attribute *ddr_perf_identifier_attrs[] = {

> > +	&ddr_perf_identifier_attr.attr,

> > +	NULL,

> > +};

> > +

> > +static struct attribute_group ddr_perf_identifier_attr_group = {

> > +	.attrs = ddr_perf_identifier_attrs,

> > +};

> > +

> >   enum ddr_perf_filter_capabilities {

> >   	PERF_CAP_AXI_ID_FILTER = 0,

> >   	PERF_CAP_AXI_ID_FILTER_ENHANCED,

> > @@ -237,6 +278,7 @@ static const struct attribute_group *attr_groups[] = {

> >   	&ddr_perf_format_attr_group,

> >   	&ddr_perf_cpumask_attr_group,

> >   	&ddr_perf_filter_cap_attr_group,

> > +	&ddr_perf_identifier_attr_group,

> >   	NULL,

> >   };

> >

> >
diff mbox series

Patch

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index 4f063fb1c6b4..3517d2fb1469 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -50,6 +50,7 @@  static DEFINE_IDA(ddr_ida);
 
 struct fsl_ddr_devtype_data {
 	unsigned int quirks;    /* quirks needed for different DDR Perf core */
+	const char *identifier;	/* system PMU identifier for userspace */
 };
 
 static const struct fsl_ddr_devtype_data imx8_devtype_data;
@@ -58,13 +59,32 @@  static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
 	.quirks = DDR_CAP_AXI_ID_FILTER,
 };
 
+static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
+	.quirks = DDR_CAP_AXI_ID_FILTER,
+	.identifier = "i.MX8MQ",
+};
+
+static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
+	.quirks = DDR_CAP_AXI_ID_FILTER,
+	.identifier = "i.MX8MM",
+};
+
+static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
+	.quirks = DDR_CAP_AXI_ID_FILTER,
+	.identifier = "i.MX8MN",
+};
+
 static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
 	.quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
+	.identifier = "i.MX8MP",
 };
 
 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
 	{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
 	{ .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
+	{ .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
+	{ .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
+	{ .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
 	{ .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
 	{ /* sentinel */ }
 };
@@ -84,6 +104,27 @@  struct ddr_pmu {
 	int id;
 };
 
+static ssize_t ddr_perf_identifier_show(struct device *dev,
+					struct device_attribute *attr,
+					char *page)
+{
+	struct ddr_pmu *pmu = dev_get_drvdata(dev);
+
+	return sprintf(page, "%s\n", pmu->devtype_data->identifier);
+}
+
+static struct device_attribute ddr_perf_identifier_attr =
+	__ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
+
+static struct attribute *ddr_perf_identifier_attrs[] = {
+	&ddr_perf_identifier_attr.attr,
+	NULL,
+};
+
+static struct attribute_group ddr_perf_identifier_attr_group = {
+	.attrs = ddr_perf_identifier_attrs,
+};
+
 enum ddr_perf_filter_capabilities {
 	PERF_CAP_AXI_ID_FILTER = 0,
 	PERF_CAP_AXI_ID_FILTER_ENHANCED,
@@ -237,6 +278,7 @@  static const struct attribute_group *attr_groups[] = {
 	&ddr_perf_format_attr_group,
 	&ddr_perf_cpumask_attr_group,
 	&ddr_perf_filter_cap_attr_group,
+	&ddr_perf_identifier_attr_group,
 	NULL,
 };