diff mbox series

[v2,1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite

Message ID 1606198876-3515-1-git-send-email-sibis@codeaurora.org
State Accepted
Commit 8fd01e01fd6f8ba67e4ed8c5be0ab76d06156287
Headers show
Series [v2,1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite | expand

Commit Message

Sibi Sankar Nov. 24, 2020, 6:21 a.m. UTC 
Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
since the gold cores only support frequencies upto 2.1 GHz.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---

V2:
 * Updated the lite ddr/l3 cpufreq map to have better power numbers with
   similar perf.

 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi

Comments

Doug Anderson Nov. 24, 2020, 5:55 p.m. UTC | #1 
Hi,

On Mon, Nov 23, 2020 at 10:21 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support
> frequencies upto 2.5 GHz.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)

Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
new file mode 100644
index 000000000000..d8ed1d7b4ec7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
@@ -0,0 +1,18 @@ 
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 lite device tree source
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+&cpu6_opp10 {
+	opp-peak-kBps = <7216000 22425600>;
+};
+
+&cpu6_opp11 {
+	opp-peak-kBps = <7216000 22425600>;
+};
+
+&cpu6_opp12 {
+	opp-peak-kBps = <8532000 23347200>;
+};