@@ -784,4 +784,8 @@ void __init ti_clk_init_features(void)
(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
}
+
+ /* Jitter correction only available on OMAP343X */
+ if (cpu_is_omap343x())
+ ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
}
@@ -234,6 +234,9 @@ struct ti_clk_features {
long fint_band2_min;
u8 dpll_bypass_vals;
};
+
+#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0)
+
extern struct ti_clk_features ti_clk_features;
extern const struct clkops clkops_omap2_dflt_wait;
@@ -310,7 +310,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
* Set jitter correction. Jitter correction applicable for OMAP343X
* only since freqsel field is no longer present on other devices.
*/
- if (cpu_is_omap343x()) {
+ if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
v = omap2_clk_readl(clk, dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
@@ -512,7 +512,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
return -EINVAL;
/* Freqsel is available only on OMAP343X devices */
- if (cpu_is_omap343x()) {
+ if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);
Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL has freqsel fields in its control register or not. Instead, add a new flag to the clk_features.flags and use this during runtime. Allows eventual move of the DPLL code under clock driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> --- arch/arm/mach-omap2/clock.c | 4 ++++ arch/arm/mach-omap2/clock.h | 3 +++ arch/arm/mach-omap2/dpll3xxx.c | 4 ++-- 3 files changed, 9 insertions(+), 2 deletions(-)