| Message ID | 20201119085405.556138-11-jckuo@nvidia.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v5,01/16] clk: tegra: Add PLLE HW power sequencer control | expand |
On Thu, 19 Nov 2020 16:53:59 +0800, JC Kuo wrote: > This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb > PHY driver. It is a phandle and specifier referring to the Tegra210 > pmc@7000e400 node. > > Signed-off-by: JC Kuo <jckuo@nvidia.com> > --- > v5: > replace "pmc@7000e400 node" -> with "PMC node" > v4: > new change to document "nvidia,pmc" prop > > .../devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 38c5fa21f435..b62397d2bb0c 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -54,6 +54,7 @@ For Tegra210: - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V. - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V. - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V. +- nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node. For Tegra186: - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb PHY driver. It is a phandle and specifier referring to the Tegra210 pmc@7000e400 node. Signed-off-by: JC Kuo <jckuo@nvidia.com> --- v5: replace "pmc@7000e400 node" -> with "PMC node" v4: new change to document "nvidia,pmc" prop .../devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt | 1 + 1 file changed, 1 insertion(+)