@@ -21,6 +21,7 @@
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
+ dpu0 = &dpu1;
gpio0 = &lsio_gpio0;
gpio1 = &lsio_gpio1;
gpio2 = &lsio_gpio2;
@@ -223,6 +224,318 @@
clock-output-names = "xtal_24MHz";
};
+ dc0_subsys: bus@56000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56000000 0x0 0x56000000 0x1000000>;
+
+ dc0_irqsteer: irqsteer@56000000 {
+ compatible = "fsl,imx-irqsteer";
+ reg = <0x56000000 0x10000>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_LIS_IPG_CLK>;
+ clock-names = "ipg";
+ fsl,channel = <0>;
+ fsl,num-irqs = <512>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ };
+
+ dc0_lpcg: clock-controller@56010000 {
+ compatible = "fsl,imx8qxp-lpcg-dc";
+ reg = <0x56010000 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ dc0_prg1: prg@56040000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56040000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG0_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG0_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg2: prg@56050000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56050000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG1_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG1_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg3: prg@56060000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56060000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG2_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG2_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg4: prg@56070000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56070000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG3_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG3_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg5: prg@56080000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56080000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG4_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG4_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg6: prg@56090000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x56090000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG5_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG5_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg7: prg@560a0000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x560a0000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG6_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG6_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg8: prg@560b0000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x560b0000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG7_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG7_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_prg9: prg@560c0000 {
+ compatible = "fsl,imx8qxp-prg";
+ reg = <0x560c0000 0x10000>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_PRG8_RTRAM_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_PRG8_APB_CLK>;
+ clock-names = "rtram", "apb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr1_channel1: dpr-channel@560d0000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x560d0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR0_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR0_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM0_CLK>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_BLIT0>;
+ fsl,prgs = <&dc0_prg1>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr1_channel2: dpr-channel@560e0000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x560e0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR0_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR0_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM0_CLK>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>;
+ fsl,prgs = <&dc0_prg2>, <&dc0_prg1>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr1_channel3: dpr-channel@560f0000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x560f0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR0_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR0_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM0_CLK>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_FRAC0>;
+ fsl,prgs = <&dc0_prg3>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr2_channel1: dpr-channel@56100000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56100000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR1_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR1_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM1_CLK>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO0>;
+ fsl,prgs = <&dc0_prg4>, <&dc0_prg5>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr2_channel2: dpr-channel@56110000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56110000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR1_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR1_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM1_CLK>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_VIDEO1>;
+ fsl,prgs = <&dc0_prg6>, <&dc0_prg7>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dc0_dpr2_channel3: dpr-channel@56120000 {
+ compatible = "fsl,imx8qxp-dpr-channel";
+ reg = <0x56120000 0x10000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DPR1_APB_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DPR1_B_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_RTRAM1_CLK>;
+ clock-names = "apb", "b", "rtram";
+ fsl,sc-resource = <IMX_SC_R_DC_0_WARP>;
+ fsl,prgs = <&dc0_prg8>, <&dc0_prg9>;
+ power-domains = <&pd IMX_SC_R_DC_0>;
+ status = "disabled";
+ };
+
+ dpu1: dpu@56180000 {
+ compatible = "fsl,imx8qxp-dpu";
+ reg = <0x56180000 0x40000>;
+ interrupt-parent = <&dc0_irqsteer>;
+ interrupts = <448>, <449>, <450>, <64>,
+ <65>, <66>, <67>, <68>,
+ <69>, <70>, <193>, <194>,
+ <195>, <196>, <197>, <72>,
+ <73>, <74>, <75>, <76>,
+ <77>, <78>, <79>, <80>,
+ <81>, <199>, <200>, <201>,
+ <202>, <203>, <204>, <205>,
+ <206>, <207>, <208>, <0>,
+ <1>, <2>, <3>, <4>,
+ <82>, <83>, <84>, <85>,
+ <209>, <210>, <211>, <212>;
+ interrupt-names = "store9_shdload",
+ "store9_framecomplete",
+ "store9_seqcomplete",
+ "extdst0_shdload",
+ "extdst0_framecomplete",
+ "extdst0_seqcomplete",
+ "extdst4_shdload",
+ "extdst4_framecomplete",
+ "extdst4_seqcomplete",
+ "extdst1_shdload",
+ "extdst1_framecomplete",
+ "extdst1_seqcomplete",
+ "extdst5_shdload",
+ "extdst5_framecomplete",
+ "extdst5_seqcomplete",
+ "disengcfg_shdload0",
+ "disengcfg_framecomplete0",
+ "disengcfg_seqcomplete0",
+ "framegen0_int0",
+ "framegen0_int1",
+ "framegen0_int2",
+ "framegen0_int3",
+ "sig0_shdload",
+ "sig0_valid",
+ "sig0_error",
+ "disengcfg_shdload1",
+ "disengcfg_framecomplete1",
+ "disengcfg_seqcomplete1",
+ "framegen1_int0",
+ "framegen1_int1",
+ "framegen1_int2",
+ "framegen1_int3",
+ "sig1_shdload",
+ "sig1_valid",
+ "sig1_error",
+ "cmdseq_error",
+ "comctrl_sw0",
+ "comctrl_sw1",
+ "comctrl_sw2",
+ "comctrl_sw3",
+ "framegen0_primsync_on",
+ "framegen0_primsync_off",
+ "framegen0_secsync_on",
+ "framegen0_secsync_off",
+ "framegen1_primsync_on",
+ "framegen1_primsync_off",
+ "framegen1_secsync_on",
+ "framegen1_secsync_off";
+ clocks = <&dc0_lpcg IMX_DC0_LPCG_DC_AXI_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DC_CFG_CLK>,
+ <&clk IMX_DC0_PLL0_CLK>,
+ <&clk IMX_DC0_PLL1_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DISP0_CLK>,
+ <&dc0_lpcg IMX_DC0_LPCG_DISP1_CLK>;
+ clock-names = "axi", "cfg", "pll0", "pll1",
+ "disp0", "disp1";
+ power-domains = <&pd IMX_SC_R_DC_0>,
+ <&pd IMX_SC_R_DC_0_PLL_0>,
+ <&pd IMX_SC_R_DC_0_PLL_1>;
+ power-domain-names = "dc", "pll0", "pll1";
+ fsl,dpr-channels = <&dc0_dpr1_channel1>,
+ <&dc0_dpr1_channel2>,
+ <&dc0_dpr1_channel3>,
+ <&dc0_dpr2_channel1>,
+ <&dc0_dpr2_channel2>,
+ <&dc0_dpr2_channel3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_disp0_pixel_combiner_ch0: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ dpu_disp1_pixel_combiner_ch1: endpoint {
+ };
+ };
+ };
+ };
+ };
+
adma_subsys: bus@59000000 {
compatible = "simple-bus";
#address-cells = <1>;
This patch adds basic i.MX8qxp DC0 subsystem support, which includes the irqsteer, LPCG clock controller, Display Processing Unit(DPU) and it's prefetch engines - Prefetch Resolve Gaskets(PRG) and Display Prefetch Resolve Channels(DPRC). Note that the clocks are still referenced in the legacy way instead of the new "two cells" binding way. So, prone to update as soon as the SoC device tree is converted to follow the new way. Signed-off-by: Liu Ying <victor.liu@nxp.com> --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 313 +++++++++++++++++++++++++++++ 1 file changed, 313 insertions(+)