@@ -3444,14 +3444,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_pl(env);
unsigned int target_el = 1;
+ unsigned int target_mode;
bool route_to_el2 = false;
- /* FIXME: Use actual secure state. */
- bool secure = false;
- if (!env->aarch64) {
- /* TODO: Add EL2 and 3 exception handling for AArch32. */
- return 1;
- }
+ bool secure = arm_is_secure(env);
if (!secure
&& arm_feature(env, ARM_FEATURE_EL2)
@@ -3473,18 +3469,10 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
}
break;
case EXCP_FIQ:
- case EXCP_IRQ: {
- const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO;
- const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ;
-
- if (!secure && (env->cp15.hcr_el2 & hcr_mask)) {
- target_el = 2;
- }
- if (env->cp15.scr_el3 & scr_mask) {
- target_el = 3;
- }
- break;
- }
+ case EXCP_IRQ:
+ target_el = arm_phys_excp_target_el(cs, &target_mode, excp_idx,
+ cur_el, secure);
+ break;
case EXCP_VIRQ:
case EXCP_VFIQ:
target_el = 1;